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上一章 介绍

2 Netlist ECO Flows

2.1 Automatic Full-Layers ECO Flow
2.1.1 Overview
2.1.2 Files and data requirements
2.1.3 Steps to do automatic functional ECO
2.1.4 Automatic Functional ECO example script
2.1.5 High Effort ECO
2.1.6 Run and debug
2.1.7 Partial Mode
2.1.8 Incremental Mode
2.1.9 Exclude Test Logic
2.1.10 No Exact Pin Match
2.1.11 Flip-flop Phase Inverted
2.1.12 Dedicated Logic Equivalence Check Engine
2.1.13 Stitch new flops into scan chain
2.1.14 Add a new module
2.1.15 Note in RTL modification and re-synthesis
2.1.16 Check design after ECO
2.2 Automatic Metal Only ECO Flow
2.2.1 Overview
2.2.2 Files and data requirements
2.2.3 Steps to do automatic Metal Only ECO
2.2.4 Example GofCall script for Metal Only ECO
2.2.5 Run and debug
2.2.6 Gated clocks in AutomaticMetal Only ECO
2.3 Script Mode Full Layers Manual ECO Flow
2.3.1 Overview
2.3.2 Steps to do Manual ECO In Scripts
2.3.3 Locate ECO point
2.3.4 Files and data requirements
2.3.5 ECO APIs list
2.3.6 Example GofCall script for Manual ECO
2.3.7 Run and debug
2.3.8 Handle repetitive work
2.3.9 Special character
2.4 Script Mode Metal Only Manual ECO Flow
2.4.1 Overview
2.4.2 Files and data requirements
2.4.3 Example GofCall script for Manual Metal Only ECO
2.4.4 Run and debug
2.5 GUI Mode Full Layers ECO Flow
2.5.1 Overview
2.5.2 Start up GOF in GUI Mode
2.5.3 Create Partial Schematic
2.5.4 Do ECO on schematic
2.5.5 Save ECO
2.6 GUI Mode Metal Only ECO Flow
2.6.1 Overview
2.6.2 Methods for Metal Only ECO
2.6.3 Setup and use cases

2.1 Automatic Full-Layers ECO Flow

2.1.1 Overview

Full layers functional ECO can add or delete gates freely. The ECO operations are done in a GofCall script which is compatible with Perl, and it uses exported APIs to access the netlist database. GOF reads in two netlist files, Implementation Netlist which is under ECO and Reference Netlist which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist. In the GofCall script, the top down API 'fix_design' is used to fix the top level module and its sub-modules in global mode. GOF uses the built-in Logic Equivalent Check Engine to figure out the non-equivalent points. And optimized minimum size gate patches are applied to fix the non-equivalent modules.

As shown in Figure 1, two logic cones are extracted from the implementation and reference netlist for the same compare point. The implementation point mismatches the reference point initially. GOF compares the two points and generated a patch from Reference logic cone and applies to Implementation Netlist. After the patching, the two points become equivalent.

img

Figure 1: Logic Cone Optimization

GOF does logic cone analysis and optimization for each failing point found in top down logic equivalence check. The failing point is in format of output port or sequential element's input pin, such as flop's D input. The final patch has the minimum number of gates to make the implementation logic cone equal to the reference logic cone.

The flow chart is shown in Figure 2.

img

Figure 2: Automatic functional ECO flow

2.1.2 Files and data requirements

2.1.3 Steps to do automatic functional ECO

A typical situation for an automatic functional ECO:

2.1.4 Automatic Functional ECO example script

The GofCall script has exact the same syntax of Perl script. It can execute exported APIs that access the netlist database and modify the netlist.

The following is an example script for an automatic functional ECO:

# GofCall ECO script, run_example.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.1.5 High Effort ECO

When set_high_effort is run, the Cutpoint Method is enabled to run ECO in high effort mode. When an ECO involves one combinational wire change, the Cutpoint Method can produce very small patch. The Cutpoint Method high ECO effort takes relatively longer time.

# GofCall ECO script, run_example_cutpoint_en.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_high_effort;
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.6 Run and debug

The GofCall Script can be run by '-run' option.

gof -run run_example.pl

Check Run and debug GofCall script section for more detail

2.1.7 Partial Mode

If all RTL changes are known to be contained in one sub-block and its sub-modules, the top level scope can be set to the sub-block. 'fix_design' can apply to the block and its sub-modules.

img

Figure 3: Partial Mode

For example, the above design has only MPU/HBUS/MEM modified. The top level can be set to MPU by 'set_top("MPU")'

# GofCall ECO script, run_example_partial.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("MPU");# Set the top module to MPU instead of the most top module SOC_TOP
fix_design;
set_top("SOC_TOP"); # Set the top module to the most top module
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.1.8 Incremental Mode

User can choose to fix the selected modules in implementation netlist, when RTL changes are known to be isolated inside the specified modules.

img

Figure 4: Incremental Mode

For example, the above design has only two modules modified, WIFI and ENC, and the changes are isolated in these two modules not propagating through hierarchical ports.

ECO API, 'fix_modules' can be run on these two modules.

# GofCall ECO script, run_example_incremental.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
fix_modules("WIFI", "ENC");
set_top("SOC_TOP");# Set the top module to the most top
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.1.9 Exclude Test Logic

Some logic in netlist should be ignored in Logic Equivalence Check and ECO, for example, DFT logic or MBIST logic. Several APIs can be used for the excluding purpose, set_ignore_output, set_pin_constant.

For example, the SOC_TOP design should have scan insertion test logic excluded in ECO. The scan out bus pin has naming of scan_out[199:0] and API set_ignore_output can be used to exclude LEC check on scan_out in ECO. And scan_enable and scan_mode are two scan set up signals which can be forced to zeros by API set_pin_constant.

# GofCall ECO script, run_example_exclude_test_logic.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.1.10 No Exact Pin Match

Physical Synthesis is more and more popular in logic synthesis. Physical Synthesis may add hierarchical pins that are not in RTL code and it may bring mapping issue when Implementation Netlist is comparing with Reference Netlist. API set_noexact_pin_match can be used to resolve the mapping issue between Implementation Netlist and Reference Netlist.

For example, some physical synthesis tool adds 'IN1', 'IN2' ... to hierarchical modules. The new added pins are not necessarily matching to each other in Implementation Netlist and Reference Netlist. They need to be excluded in pin matching. API set_noexact_pin_match is used before loading design.

# GofCall ECO script, run_example_noexact_pin_match.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
set_noexact_pin_match('\bIN\d+\b'); # The argument is in REGEX format
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.1.11 Flip-flop Phase Inverted

Place and Route tool may invert some flip-flops' phase by moving inverter from input pin to output pin. API set_mapping_method('-phase') is used to handle these flip-flops.

# GofCall ECO script, run_example_ff_phase_inverted.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
set_mapping_method('-phase');
fix_design;
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter
exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.1.12 Dedicated Logic Equivalence Check Engine

The built-in Logic Equivalence Check Engine is dedicated to search equivalent nets in Implementation Netlist to optimize the patch circuit. The searching process is global.

img

Figure 5: Dedicated LEC Engine

For each net in the Reference Logic Cone, any net in the Implementation Logic Cone with the same fanin end-points is compared for Logic Equivalence.

Users can check equivalence on any two nets in the reference and implementation netlists. The API 'comare_nets' can be used to compare any two nets in Reference Netlist and Implementation Netlist.

Compare_nets API:

Check equivalence of two nets in the reference and implementation netlist

Usage: my $result = compare_net($net0, $net1);
$net0: The net in Reference Netlist.
$net1: The net in Implementation Netlist.
$result: If 1, they are equal, if 0, they are not equal.
Examples:
# Compare reg1/D in the reference and reg1/D in Implementation Netlist
compare_nets("reg1/D", "reg1/D");

2.1.13 Stitch new flops into scan chain

Scan chain can be updated to insert the new flops. 'stitch_scan_chain' command can be used to automatically stitch up the new flops.

For example, eight new flops 'state_new_reg_0' to 'state_new_reg_7' are added in fix_design command. To insert them to the scan chain before 'pulse_reg'

stitch_scan_chain('-to', 'pulse_reg');

The scan chain can be reconnect up by manual change_pin commands as well.

2.1.14 Add a new module

The module mentioned in the section above can have hierarchy kept instead of flatten, and being written into ECO netlist as whole. This flow needs the module and its sub-modules written out in a separate verilog file, then uses read_library to load the file with '-vmacro' option. GOF treats the module as a leaf cell.

An example for adding a new module:

# GofCall ECO script, run_new_module_example.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_hier_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_library("-vmicro", "syn_macro.v");
read_design("-ref", "reference.gv");# Read in the Reference Netlist
# Read in the implementation netlist which is under ECO
read_design("-imp", "implementation.gv");
set_top('top');# Set the top module
fix_design;
report_eco();# ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter

The content in file syn_macro.v is written into the ECO file eco_verilo.v as a whole. The corresponding instance is created as well with ports connected correctly according to Reference Netlist.

2.1.15 Note in RTL modification and re-synthesis

When modifying RTL and do re-synthesis, care should be taken to maintain the database as much alike Implementation Netlist as possible.

2.1.15.1 Keep sequential signal name

A common problem in modifying RTL is having sequential signal name changed, which appears in Reference Netlist as a different flop instance. For example

always @(posedge clk) abc <= abc_next;

It creates a flop instance 'abc_reg' in synthesis. If the ECO in RTL change this to

always @(posedge clk) abc_new <= abc_next;

After synthesis, a new flop instance 'abc_new_reg' is created. GOF may fail to find that 'abc_new_reg' being able to merge with 'abc_reg', due to other non-equivalent points present, which brings a redundant fix in the new register creation.

So it is highly recommended to keep the sequential signal names.

2.1.15.2 Use the same synthesis constraints

When do re-synthesis, the same constraints should be used as what has been used in Implementation Netlist synthesis. If any hierarchy is not present in Implementation Netlist, flattening command should be used in synthesis to flatten the module to the maintain the same hierarchies.

2.1.16 Check design after ECO

It is highly recommended to run 'check_design' after ECO, to speed up, users can specify '-eco' option,

check_design('-eco')

It can detect if there is any floating or multiply drivers after ECO.

2.2 Automatic Metal Only ECO Flow

2.2.1 Overview

In Metal Only ECO, the design has completed place and route. Any new gates added should map to spare gates that located in the design.

img

Figure 6: Metal Only ECO

The flow can use internal synthesis engine or external synthesis tool to map patch logic to spare types. It requires one of the spare type combinations as the following

A Design Exchange Format file is needed to map new instances to the closest spare gate instances. If DEF file is not loaded, GOF processes the ECO with gates type from the spare list without mapping to the exact spare instances. P&R tool like SOC Encounter maps the new instances in the new netlist to the closest spare gates.

In 'fix_design' command, GOF analyzes the top level module and its sub-modules to isolate the non-equivalent points and optimize the logic cone to find the minimum gate count patch circuit.

The flow can use external Synthesis Tool as well. The executable synthesis command should be in the search path. The supported Synthesis Tool is RTL Compiler from Cadence and Design Compiler from Synopsys.

GOF writes out the patch in Verilog file and a TCL script for external Synthesis Tool if it's enabled. The TCL script is to constrain the Synthesis Tool to use spare gates only when remapping the gates in the patch file. The Synthesis Tool is run with the Verilog file and TCL script as inputs, and it writes out remapped Verilog patch file which has only spare gate types.

When the spare-only patch file is created, user can pause the flow by '-pause' in 'map_spare_cells' command. User can either modify the patch file manually or tunes up the constraint file to rerun the synthesis for several iterations until the patch netlist meets the requirement. Then press 'n' key to resume the flow.

GOF reads back the spare-only patch file and fits the circuit into Implementation Netlist to fix the logic cones.

When ECO is done, a report can be created and ECO netlist/ECO script can be written out for the back end tool and LEC tool.

2.2.2 Files and data requirements

2.2.3 Steps to do automatic Metal Only ECO

A typical process for an automatic Metal Only ECO:

2.2.4 Example GofCall script for Metal Only ECO

The GofCall script has the exact same syntax of Perl script. But it can execute exported commands that access the netlist database and modify the netlist.

The following shows an example of an automatic Metal Only ECO:

# GofCall ECO script, run_metal_only_example.pl
use strict;
undo_eco;# Discard previous ECO operations
# Setup ECO name
setup_eco("eco_metalonly_example " );

read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("topmod");# Set the top module that ECO is working on
fix_design;
# The following is metal ECO related
read_def("topmod.def");# Read Design Exchange Format file, optional
# Specify spare cell pattern, when 'map_spare_cells' is done, a new spare list file is written out
# with updated spare list.
get_spare_cells("*/*_SPARE*");
# Comment the above line and use the following line to use spare list file
# if the spare list file has been generated already and gone through other ECOs
# get_spare_cells("-file", "spare_list_file.txt");
map_spare_cells();
# Use one of the following lines if external Synthesis Tool is used
#map_spare_cells ( "-syn", "rc" );
#map_spare_cells ( "-syn", "dc_shell" );
report_eco(); # ECO report
check_design("-eco");# Check if the ECO causes any issue, like floating
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter

exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.2.5 Run and debug

The GofCall Script can be run by '-run' option.

gof -run run_metal_only_example.pl

User can insert 'die' command to let GOF stop in some point and do interactive debugs when 'GOF >' shell appears. GUI mode can be enabled by run 'start_gui' command.

Check Run and debug GofCall script section for more detail

2.2.6 Gated clocks in AutomaticMetal Only ECO

If the automatic metal only ECO has new gated clock cells added while the spare gates list doesn't have gated clock cell, "convert_gated_clocks" API should be run to convert gated clock cells to 'MUX' type logic. GOF maps the 'MUX' type logic to the spare type gates in 'map_spare_cells' API.

get_spare_cells("*/*_SPARE*");
Convert_gated_clocks();
map_spare_cells();

2.3 Script Mode Full Layers Manual ECO Flow

2.3.1 Overview

In many cases, the ECO operations are well known by users. They can be inserting buffers to a 128bits bus, or adding isolation AND gates to all outputs of a module. In these cases, manual ECO by scripts is more efficient and resource saving.

GOF exports many APIs for ECO operations in GofCall script.

2.3.2 Steps to do Manual ECO In Scripts

A typical situation for a Manual ECO:

2.3.3 Locate ECO point

Locating ECO point is the hardest part in manual ECO. Wire names in RTL codes are normally optimized away by synthesis process. GOF has a feature to retrieve the nets. Check here for the GUI way or use API 'get_match_nets' in GofCall script.

2.3.4 Files and data requirements

2.3.5 ECO APIs list

These APIs change Implementation Netlist

For the full list of the APIs, user can type 'help' in 'GOF >' shell.

For the individual API, type 'help api_name' . For example:

GOF > help new_port
Help for new_port
new_port: ECO command. Create a new port for the current top level module
ECO command. Create a new port for the current top level module
Usage: new_port($name, @options);
$name: Port name
@options:
-input: New an input port
-output: New an output port
-inout: New an inout port
Note: The port name has to be pure words or with bus bit, like, abc[0], abc[1]
Examples:
new_port('prop_control_en', '-input'); # create an input port naming 'prop_control_en'
new_port('prop_state[2]', '-output'); # create an output port with bus bit 'prop_state[2]'
new_port('prop_state[3]', '-output'); # create an output port with bus bit 'prop_state[3]'

2.3.6 Example GofCall script for Manual ECO

# GofCall ECO script, run_example.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in implementation Netlist Which is under ECO
set_top("topmod");# Set the scope to the module that ECO is working on

# The following API adds a mux in flop 'state_reg_0_' D input pin,
# and connect up the original connection to pin 'A',
# pin 'B' connect to net 'next_state[7]', and pin 'S' to net 'sel_mode'
# the net can be replaced by format of 'instance/pin' , E.G. '.S(state_reg_2_/Q)'
change_pin("state_reg_0_/D", "MX2X4", "", ".A(-),.B(next_state[7]),.S0(sel_mode)");

report_eco();
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter

exit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.3.7 Run and debug

Check Run and debug GofCall script section for more detail

2.3.8 Handle repetitive work

A Perl 'for' or 'foreach' loop can handle repetitive work efficiently. For example, to add a 'AND' isolation gate for every output port of a module.

# GofCall ECO script, add_ands.pl
use strict;
undo_eco;# Discard previous ECO operations
setup_eco("eco_example");# Setup ECO name
read_library("art.90nm.lib");# Read in standard library
read_design("-ref", "reference.gv");# Read in Reference Netlist
read_design("-imp", "implementation.gv");# Read in implementation Netlist which is under ECO
set_top("topmod");# Set the top module that ECO is working on
my @ports = get_ports("-output");# Get all output ports of module 'topmod'
# For each output port of 'topmod', insert an 'AND' gate to enable it only when 'enable_out' is high
foreach my $port (@ports){
  change_port($port, "AND2X2", "", "-,enable_out");
}

report_eco();
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
write_soce("eco_soce.tcl");# Write out TCL script for SOC Encounter

gexit;# Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

2.3.9 Special character

The special character '-' is used to represent existing connection. For example

change_pin("U0/A", "BUFFX1", "eco_buf","-");

A buffer is inserted into A pin of instance U0. The old existing net drives the new buffer now.

The special character '.' is used in ECO new instance name if the new instance needs to be in the same hierarchy as the ECO spot.

change_pin("u_qcif/u_num2/u_spare1/B", "AOI21X2",".", "net1,net2,net3");

If the instance is empty, GOF creates 'AOI21X2' in the current top level. With ".", GOF creates 'AOI21X2' new instance in hierarchy "u_qcif/u_num2/u_spare1".

2.4 Script Mode Metal Only Manual ECO Flow

2.4.1 Overview

In Manual Metal Only ECO, any new added gates are automatically mapped to spare gate instances by 'map_spare_cells' command. A Design Exchange Format file has to be loaded for the tool to find optimal spare instances. If the file is not present, the mapping is skipped.

2.4.2 Files and data requirements

2.4.3 Example GofCall script for Manual Metal Only ECO

# Manual Metal Only ECO, manual_metal_eco.pl
use strict;
undo_eco;
setup_eco("metal_eco0123");
set_log_file("metal_eco0123.log");
read_library("/prj/lib/tsmc40.lib");
read_design("-imp", "/prj/netlist/imp_net.v");
set_top("mtop");

new_port("nout7", "-output");# Create a new port 'nout7'
# Place the port to 60000, 1000000. It's approximate position, the main purpose is for
# spare instances selection
place_port("nout7", 60000, 100000);
new_port("nout8", "-output");# Create another port
place_port("nout8", 120000, 81000);
# 'nout8' is driven by an invert first, and the invert's input is driven by pin 'cmpmod/rego/QN'
change_port("nout8", "INV_X1M", "", "cmpmod/rego/QN");
# Drive the 'nout7' by 'INV_X1M' and leave the input unconnected, but the mapped
# spare instance name is returned.
my $inst = change_port("nout7", "INV_X1M", "", "");
# Drive the new instance's input by a flop, and specify the flop's connection in the 4<sup>th</sup>argument
change_pin("$inst/A", "SDFFRPQ_X4M", "", \
".CK(cmpmod/rego/CK),.D(cmpmod/rego/QN),.R(1'b0),.SE(1'b0),.SI(1'b0)");

read_def("/prj/def/imp_net.def");
get_spare_cells("Spare_*/*_SPARE_GATE*");
# Before mapping to spare gates, set a large number in buffer distance, so that GOF does not
# add buffers for long connections.
set_buffer_distance(9999999);
# The following 'map_spare_cells' command maps the three new ECO instances to the optimal
# spare instances.
map_spare_cells;

report_eco;
write_verilog("imp_eco0123.v");

2.4.4 Run and debug

The GofCall Script can be run by '-run' option.

gof -run manual_metal_eco.pl

Check Run and debug GofCall script section for more detail

2.5 GUI Mode Full Layers ECO Flow

2.5.1 Overview

The following paragraph demonstrates how to insert buffers and inverters into a circuit in GUI mode.

2.5.2 Start up GOF in GUI Mode

Start up Gates On the Fly by the command line

gof -lib t65nm.lib -lib io.lib netlist_port.v

For detail usage, visit this link

https://nandigits.com/usage.htm

In GofViewer netlist window, press ctrl-g or menu commands->'Launch GofTrace with gate'. Fill in the instance name that needs ECO.

img

Figure 7: Load gate to schematic

2.5.3 Create Partial Schematic

In GofTrace schematic window, use mouse middle button to expand the schematic. In this case, pin D of the flop should be inserted an invert.

img

Figure 8: Partial Schematic for GUI ECO

2.5.4 Do ECO on schematic

Check ECO button to enable ECO mode

img

Figure 9: Schematic in ECO Mode

Press mouse-left-button on the wire to select it. Click ECO button 'Insert gates into connections', select the right invert in the gate type selection window.

img

Figure 10: Select Gate in GUI ECO

In 'Pin Connections' setup window, use default 'Complete Loop' option, so that the gate can be inserted in the net.

img

Figure 11: New Cell Pin Connection Selections

Click OK and the invert is inserted.

img

Figure 12: Manual ECO with New Gate Inserted

2.5.5 Save ECO

Press ECO button 'Save ECO result to file'. And select the format to be saved. The supported formats include verilog netlist, SOC Encounter ECO script, GofCall Script, TCL script and DCShell script.

img

Figure 13: Save ECO in GUI Mode

2.6 GUI Mode Metal Only ECO Flow

2.6.1 Overview

Metal ECO can only use existing spare gates on the silicon. Gates On the Fly controls how to use these spare gates.

2.6.2 Methods for Metal Only ECO

Four methods are supported in Metal Only ECO:

  1. User can add any type of gates and let the tool map to the spare type gates, Place and Route tool should map the spare type gates to the exact spare gate instances.
  2. User can add any type of gates and let the tool map to the exact spare gate instances.
  3. User can add only spare type gates and let the tool map to the exact spare gate instances.
  4. User can pick the exact spare gate instances, and connect and disconnect up the instances in ECO.

Note: 'Spare type gate' refers to the gate type, 'INVX2', 'NAND2X2'. 'Exact spare gate instance' refers to the spare instances in the design, E.G. 'spare1/spare_invx2'

2.6.3 Setup and use cases

The detail setup for four method can be found in GofECO Metal Only ECO. Use cases can be found in online document.

下一章 脚本模式

位置:文档/GOF用户手册/第二章 网表ECO流程

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