The GOF platform features a built-in powerful logic equivalence checker tool called GOF LEC. While not mandatory, the tool can benefit from SVF files in certain cases. It is strongly advised to utilize SVF files if they are obtainable, especially for designs with multibit flop. The two designs being compared can either be in RTL or Netlist format, with RTL supporting SystemVerilog2017. The read design method differs depending on whether RTL or Netlist is being supported.
Figure 1: GOF LEC Engine
The following is the example script for Netlist to Netlist LEC:
The following is the example script for RTL to Netlist LEC:
