# filename: goflec.pl
# run: gof -run goflec.pl
use strict;
set_log_file("goflec.log");
# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");
# read ref. netlist
read_design("-ref", "top_syn.v");
# read imp. netlist
read_design("-imp", "top_pr.v");
# set top module
set_top("top_module_name");
# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
# optional, remove comments when phase inversion detection enabled
#set_mapping_method("-phase");
run_lec();
# filename: gofeco.pl
# run: gof -run gofeco.pl
use strict;
set_log_file("gofeco_premask.log");
# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");
# read ref. netlist
read_design("-ref", "top_syn.v");
# read imp. netlist
read_design("-imp", "top_pr.v");
# set top module
set_top("top_module_name");
# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
# eco
fix_design();
# report and write result
report_eco();
write_verilog("top_pr_eco.v");
# filename: gofeco.pl
# run: gof -run gofeco.pl
use strict;
set_log_file("gofeco_postmask.log");
# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");
# read ref. netlist
read_design("-ref", "top_syn.v");
# read imp. netlist
read_design("-imp", "top_pr.v");
# set top module
set_top("top_module_name");
# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
# premask eco
fix_design();
report_eco();
# postmask eco
read_def("top.def");
get_spare_cells("spr_1/spr_gate*");
map_spare_cells();
report_eco();
# report and write result
write_verilog("top_pr_eco.v");
# filename: gofdebug.pl
# run: gof -run gofdebug.pl
use strict;
set_log_file("gofdebug.log");
# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");
# read netlist
read_design("top_netlist.v");
# set top module
set_top("top_module_name");
start_gui();
# filename: gofdebug.pl
# run: gof -run gofdebug.pl
use strict;
set_log_file("gofdebug.log");
# read libraries
read_library("stdcell.lib");
read_library("sram.lib");
read_library("analog.lib");
# read ref. netlist
read_design("-ref", "top_syn.v");
# read imp. netlist
read_design("-imp", "top_pr.v");
# set top module
set_top("top_module_name");
# bypass test mode if exists
set_ignore_output("scan_out*");
set_pin_constant("scan_enable", 0);
set_pin_constant("scan_mode", 0);
run_lec();
start_gui();
在ECO脚本或者LEC脚本的最后,加上write_compare_points
和write_formality_help_files
API。
# ...
run_lec();
write_compare_points("gof_compare_points.rpt");
write_formality_help_files("fm_20240103");
运行后,在目录下生成fm_20240103_config.tcl
,在formality signoff LEC脚本match
命令之前加上source -echo -verbose fm_20240103_config.tcl
,例如:
read_db ...
read_verilog -r -05 { resyn.v }
set_top r:/WORK/top
read_verilog -i -05 { eco.v }
set_top i:/WORK/top
# bypass dft
# source help file from gof
source -echo -verbose fm_20240103.config.tcl
match
verify