NanDigits

GOF APIs

Summary

Detail Usage

add_mapped_instance

Add mapped instance pair between REF and IMP

Usage:
add_mapped_instance($ref_instance, $imp_instance);

Examples:
add_mapped_instance("u_subtop/u_def/state_reg", "u_subtop/uinst_def/state_reg");

buffer

ECO command. Buffer high fanout ECO nets

Usage:
buffer($net_names, $buffer_name, $fanout);
$net_names: Net names to be buffered. Use "," to separate multiple nets, like "eco1_net1,reset2"
$buffer_name: The buffer module name from library, leave it blank to let the tool pick one.
              It supports repeater case by ",", for example, "INVX1,INVX16" would have 'INVX1'
              drives 'INVX16' and 'INVX16' drives the fanouts.
$fanout: How many fanout to insert a buffer.


Examples:
#1. For every 10 fanout of test_mode, add a buffer, BUFX6
buffer("test_mode", "BUFX6", 10); 

#2. For every 10 fanout of 'clock', add repeaters, INVX2,INVX16
buffer("clock", "INVX2,INVX16", 10);

#3. Let the tool pick a buffer
buffer("clock", "", 10);

change_gate

ECO command. Modify an instance in ECO
Two types of usages

Usage1:
change_gate($instance, $new_reference, $pin_mapping);
$instance: The instance under ECO. Support hierarchical name, "u_abc/U123"
$new_reference: The new reference name which the instance changes to, E.G. 'AND3X1'. 
                If no reference is present, the ECO operation is assumed to 
                  change the instance's pin connections.
$pin_mapping: Input pins mapping, ".new(old)", E.G. ".A1(A),.B1(B)"
              if two references have same input pins. The option can be empty

Usage2:
change_gate($instance, $pin_connections);
$pin_connections: New pin connections, ".A(n242)".
                  The unspecified pins keeps the original connection.
                  E.G. pin 'B' connection is unchanged.


Examples:
#1. U123 has reference OR3X1 with input pins, A,B,C originally
# change U123 to AND3X1, all input pins are the same.
change_gate('U123', 'AND3X1', ""); 

#2. A and B keep the connections, discard C
change_gate('U123', 'AND2X1', "");

#3. A keeps the connections, B connects to what the old C connects. And discard old B
change_gate('U123', 'AND2X1', ".B(C)"); 

#4. A,B,C keep the same, and new D pin connects to net n123
change_gate('U123', 'AND4X1', ".D(n123)"); 

#5. AO21X1 has input pins, A0, A1 and B0 
change_gate('U123', 'AO21X1', ".A0(A),.A1(B),.B0(C)");

#6. change U123 A to n123, B to n124, keep C connection. 
change_gate("U123", ".A(n123),.B(n124)"); 

#7. Rotating A/B/C connections.
change_gate("U123", ".A(B),.B(C),.C(A)");

change_net

ECO command. Change a existing net's driver

Usage:
change_net($net, $gate, $instance, $connections);
$net: The net to be ECOed
$gate: New leaf gate to drive the net
$instance: The instance name of the new gate. Optional, if it is empty, assigned by the tool
$connections:  The new gate input pins connections. If it is empty, the gate is inserted in the net
   Supported formats, 1. Very detail  ".A(net0),.B(net1),.C(net2)"
                      2. Connect to the pins in alphabetical sequence 
                          "net1,net0,net2" indicating A->net1,B->net0,C->net2
                      3. Other instance/pin "U408/Y,U409/Y,net2" indicating A->U408/Y,B->U409/Y,C->net2
                      4. Special character '-' is used to connect up the original connection


Examples:
#1. Drive n123 with BUFX2 driven by n40
change_net("n123", "BUFX2", "", "n40");   

#2. Drive n123 with AND2X2 driven by n40 and original n123 driver
change_net("n123", "AND2X2", "", "-,n40");    

#3. Insert a buffer into n123
change_net("n123", "BUFX2");

change_pin

ECO command. Modify pin connection of instances by inserting gates, changing connection to other signal 
Two types of usages. 


Usage1:
change_pin($pin_name, $net);
Change pin's connection to a net
$pin_name: In the format of "instance/pin", can be more than one pins separated by ",",
             "instance1/pinA,instance2/pinB", E.G. "U123/A", "U123/A,U345/B"
             Hierarchical naming style is supported as well, "u_abc/U123/A"
             The pins have to be input in this mode.
$net: The net name the pin connects to.
      Hierarchical naming style is supported, "u_abc/net123"
      When the pin and the net are in different hierarchies, ports are added automatically
      E.G. 
      # The tool creates 4 ports across the hierarchies to connect the net to the pin.
      change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/net300");
      # The tool gets the net tie to Y pin of U300 and do the the same as the previous example.
      change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/U300/Y");


Usage2:
my $inst = change_pin($pin_name, $leaf_cell, $new_instance, $connection);
Insert a new leaf cell to drive the pin
$inst: Return new instance name if new gate is created in the command.
$pin_name: In the format of "instance/pin", E.G. U123/A  Hierarchical naming is supported, u_abc/U123/A
           The pin can be output in this mode. The tool gets the net the pin drives,
             and change the command to 
             change_net($thenet, $leaf_cell, $new_instance, $connection);
$leaf_cell: The leaf cell name to drive the $pin_name
$new_instance: The instance name for the new inserted leaf cell. 
               The option is optional, the tool assigns one if it's empty
               If use '.', the instance is added to the same hierarchy as the $pin_name
$connection: The pins connection for the new cell. 
   Supported formats, 1. Detail format:  ".A(net0),.B(net1),.C(net2)"
                      2. Simple format: Connect to the pins in alphabetical sequence "net1,net0,net2"
                      3. Mixed format: "u_abc/U123/Y,.B(net1),net2"
                      4. Special character '-' is used to connect up the original connection
                      5. Advanced nesting format: 
                         change_pin("U189/A", "AOI21X2", "", "U190/Y,,BUFX6(BUFX6(BUFX6(n412)))");


Note:
All strings should be quoted by ' or " to avoid syntax error or undesired effects.
     


Examples:
#1. U123 has input pins A,B,C, U234 has input pins A0,A1,B
# Change A pin of U123 to net12345
change_pin("U123/A", "net12345"); 

#2. Change A pin of U123 to $net which is defined in the ECO script.
change_pin("U123/B", $net); 

#3. Change A pin of U123 to net12345
change_pin("U123/A,U234/B", "net12345");

#4. Insert "NAND2X2 eco12345_U0(.A(net1234),.B(net5678));"
# to drive U123/A
change_pin("U123/A", "NAND2X2", "eco12345_U0", "net1234,net5678"); 

#5. Same as above, with more detail of pin connections
change_pin("U123/A", "NAND2X2", "eco12345_U0", ".A(net1234),.B(net5678)"); 

#6.Insert a buffer to U123 A pin
change_pin("U123/A", "BUFX4", "", "-"); 

#7. Insert NAND2X1 to drive CK pin and new A connects to the original net
change_pin("abc_reg_1_/CK", "NAND2X1", "", ".A(-),.B(1'b1)"); 

#8. Do hierarchical connection
change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/U300/Y"); 

#9. Nested connection
change_pin("qcif/num2/u_spare1/B", "AOI21X2", "eco_inst_on_top1", \
           "NAND2X2(gte_344/u_smod/U100/Y, gte_344/n114), gte_343/U111, BUFX6(BUFX6(n105))");

change_port

ECO command. Change an output port's driver, or add gate after input port 

Usage1:
change_port($port, $gate, $instance, $connections);
$port: The port under ECO, can be input port or output port
$gate: New leaf gate to drive the port if the port is output
       Or add the gate after input port
$instance: The instance name for the new leaf cell, optional, the tool assigns one if it's empty
$connections: The new gate input pins connections. If it is empty, the gate is inserted in the net
   Supported formats, 1. Very detail  ".A(net0),.B(net1),.C(net2)"
                      2. Connect to the pins in alphabetical sequence 
                          "net1,net0,net2" indicating A->net1,B->net0,C->net2
                      3. Other instance/pin "U408/Y,U409/Y,net2" indicating A->U408/Y,B->U409/Y,C->net2
                      4. Special character '-' is used to connect up the original connection

Usage2:
change_port($port, $inst_pin);
$port: The port under ECO, output port
$inst_pin: In the format of 'u1234/Y', instance-name/pin-name

Note:
The difference of change_net and change_port command
      change_net changes all drains of the net.
      change_port changes only the port driver.


Examples:
#1. Add buffer to output port 'out1'
change_port("out1", "BUFX1", "eco_buf0", "-");

check_design

Check if the netlist status, searching for unresolved modules, floating and multi-drivers 

Usage:
check_design(@options);
@options:
   -ignore list: Ignore the issues matching the list, E.G. 'FE_UNCONNECT*,SCAN_*'. 
   -eco: Only check instances/wires having been done ECO. Default check all instances/wires
   -fixfile filename: Create ECO fix file
   -nouniquify: Dont check uniquify


Examples:
check_design;
check_design('-ignore', 'FE_UNCONNECT*');
check_design('-ignore', 'FE_UNCONNECT*,SCAN_*');
check_design('-ignore', 'W-108');
check_design("-eco");

compare

Logic equivalence check on output port and register input pins

Usage:
my $no_eq_num = compare(@nets, @options);
@options:
   -help: Print this info
$no_eq_num: Return back non-equivalent number


Examples:
#1. Check if output port 'state_out' is equivalent in IMP/REF netlists
compare("state_out");

#2. Check two points at the same time.
    Check if 'state_reg_0_/D' is equivalent in IMP/REF netlists
    And check if 'state_reg_1_/D' are equivalent in IMP/REF netlists
compare("state_reg_0_/D", "state_reg_1_/D");

compare_nets

Check equivalence of two nets in the reference and implementation netlist

Usage:
my $result = compare_nets($net0, $net1, @options);
$net0: The net in the reference netlist.
$net1: The net in the implementation netlist.
@options:
$result: 1, they are equal, 
         0, they are not equal.


Examples:
#1 Compare reg1/D in the reference and reg1/D in the implementation netlist
compare_nets("reg1/D", "reg1/D");

convert_gated_clocks

ECO command. Convert gated clocks to MUX logic.
In metal ECO, if gated clock cell is not in spare gate list, this command should run before map_spare_cells

Usage:
my $cnt = convert_gated_clocks();
$cnt: The number of gated clock cells having been converted

create_clock

Timing command and GOF Formal command. Create clock for fault verification

Usage:
create_clock($clock_name, $clock_period);
$clock_name: Clock name, input port name or black box instance output pin
$clock_period: Clock period


Note:
This command can be used multiple times. The clock period is recommended to be multiples of 2


Examples:
#1. Create clock on PIN_SPI_CLK, period 4ns
create_clock("PIN_SPI_CLK", 4);

#2. Create clock on PIN_APB_CLK and PLL clk_out
create_clock("PIN_APB_CLK", 2);
create_clock("u_pll_top/u_pll_core/clk_out", 2);

create_pin_mapping_json_file

Create pin mapping file between original synthesis netlist and pre-ECO netlist

Usage:
create_pin_mapping_json_file($filename);
$filename: JSON file name

create_reset

Create reset for the design

Usage:
create_reset($reset_name, $active_level);
$reset_name: Reset name, input port name or black box instance output pin
$active_level: The level that the reset is active


Examples:
#1. Create reset on PIN_RESETN, active low
create_reset("PIN_RESETN", 0);

#2. Create reset on PIN_RESET, active high
create_reset("PIN_RESET", 1);

current_design

Set the current top level module 

Usage:
current_design($module);
$module: Set $module as the current top level module.
         If the argument is missing, return the current setting
         ".." set to parent module, "~" set to the most top level module 

Note:
It can be reset to the root top module by 'undo_eco'. It is alias command of 'set_top'

current_instance

Set the current instance, alias of 'set_inst'

Usage:
current_instance($instance);
$instance: Set $instance as the current instance.
         If the argument is missing, return the current setting
         ".." set to parent module, "~" set to the most top level module 

Note:
It can be reset to the root top module by 'undo_eco'. It has same effect of 'set_top' and 'current_design'

del_gate

ECO command. Delete gate

Usage:
del_gate($inst);
$inst: The instance to be deleted.

del_net

ECO command. Delete net

Usage:
del_net($net);
$net: The net to be deleted.

del_port

ECO command. Delete port

Usage:
del_port($port);
$port: The port to be deleted.

dft_drc

DFT DRC checker

Usage:
my $error = dft_drc(@options);
$error: DRC errors in the checker
@options:
    -single: One clock for each scan chain
    -glitch: Check reset/set pin glitch


Examples:
#1. Run full DFT DRC
dft_drc;
#2. One clock for each scan chain in DRC
dft_drc("-single");
#3. Check reset/set pin glitch
dft_drc("-glitch");

do_auto_change

AI command, do automatic ECO change

Usage:
do_auto_change(@arguments);
@arguments: Automatically generated from the query in natural language

elab_rtl

Elaborate on RTL design

Usage:
elab_rtl();

elaborate

Elaborate and compile RTL files

Usage:
elaborate();

exist_inst

Check if an instance exists 

Usage:
my $ret = exist_inst($inst);
$inst: The instance for checking
$ret: 1, the instance exists 0, the instance does not exist

exist_wire

Check if a wire exists 

Usage:
my $ret = exist_wire($wire);
$wire: The wire name for checking
$ret: 1: exists 0: not exist

find_equal_nets

Find equivalent nets in IMP for the listed nets in REF, the results are printed out on the screen

Usage:
find_equal_nets(@ref_nets);
options: ("help","full=i")
   -help: Print this info


Examples:
#1. Find IMP equal nets for 'mbist_done', 'sync_start' in REF
find_equal_nets('mbist_done', 'sync_start');

fix_design

ECO command to fix the design in automatic ECO 

Usage:
fix_design(@options);
@options:
    -help: Print this information
    -opt_set optimization_set: Patch optimization set, 0: area/timing 1: cell count, default 0
    -no_patch_opt: Disable patch optimization. Also see API set_no_patch_opt
    -flatten: Enable flatten mode ECO. The default mode is hierarchical
    -list_file the_list_file: The ECO point list file converted from RTL-to-RTL LEC result
             The list file format:
                inst u_def/u_sdef/state_reg_1_
                pin  u_control/u_sreg/u_mem_128x24/A[0]
                port PORT_READY_OUT
    -iteration iteration_number: Fix design iteration by default 3 times.
          The tool repeats the fix process until there is no non-equivalent points or iteration number reached

Examples:
#1. Fix design on module 'VIDEO_TOP' and its sub-modules
set_top('VIDEO_TOP');
set_ignore_output("TEST_SO*");
set_pin_constant("TEST_EN", 0);
fix_design;
save_session("this_eco");
my $error = LEC;

#2. Do ECO in flatten mode
fix_design("-flatten");

#3. Do ECO on points listed in the file
fix_design("-list_file", $list_file);

fix_logic

ECO command. Fix listed points

Usage:
fix_logic(@pin_port_list,@options);
@options:
    -force: Force the tool to replace the logic cone of the points in @pin_port_list
@pin_port_list: 
    List of the pins or ports whose logic will be fixed by the reference logic in Reference Netlist
     The format is "sic_cnt_reg_0/D","sic_cnt_reg_1/D",'\bbr_ccd_reg[0] /D',"out_port"
     '\' should be kept if the instance has '\' as prefix. 
     E.G. '\bbr_ccd_reg[0] ' instance has '\' and last space in the name.



Examples:
#1. Fix state_regs's D inputs
fix_logic("state_reg_0/D", "state_reg_1/D");

#2. Fix state_regs's D inputs and one output port
fix_logic("state_reg_0/D", "state_reg_1/D", "out_port");

#3. Add one new flop, input pins have the same connections as the Reference Netlist
#  and the output is floating, -recover option sets to 0
fix_logic('new_flop_reg/D', 'new_flop_reg/CK', 'new_flop_reg/RB');

flatten_modules

Flatten hierarchical modules in reference netlist

Usage:
flatten_modules(@module_names);
@module_names: List of modules to be flatten


Examples:
flatten_modules("retime_1", "sync_cell_0");

get_cell_cofactors

Get combinational cell pin Shannon expansion cofactors

Usage:
@cofactors = get_cell_cofactors($cell, $pin);
$cell: Leaf cell name
$pin: Input pin name
@cofactors: Shannon cofactors for the pin of the cell
            It has two items if the cell is combinational 
            It is empty if the cell is sequential or black-box


Examples:
#1. NAND2X1 A pin 
@ret = get_cell_cofactors("NAND2X1", "A"); # @ret = (1, B);
#2. AOI222X1 A0 pin
@ret = get_cell_cofactors("OAI222X4", "A0"); 
returned @ret = ("!(A1*(B0*(C0+C1)+!B0*(B1*(C0+C1))))", "!(B0*(C0+C1)+!B0*(B1*(C0+C1)))");

get_cell_info

Get information of a module or instance 

Usage:
$data = get_cell_info($module_or_inst, @options);
$module_or_inst: The module or instance's name
@options:
    -help: Print this information
    -conns: Get Connections of the item, only when it's instance
    -type: Get the item's type information. It can be 'ff','cg,'latch','buf', 
            run 'get_lib_cells -type_info' for all existing type in the current libraries
            An array is returned if this option is present
    -libname: Get the library name that the cell is in
    -area: Get the area of the item
    -size: Get the size of the item
    -fun:  Get the function string of the item
    -leakage: Get the leakage of the item
    -ref:     Same as 'get_ref instance' if the item property is instance
    -context: Get detail library information
    -attribute attribute_name: Check if the cell has the attribute set. 0 or 1 is returned
$data: Returned data, if '-attribute' option is present, $data is 0 or 1
In option is '-conns' case,
It is a hash having the following data structure
my $module = $hash->{module};
my $instance: $hash->{instance};
foreach my $port (keys %{$hash->{connections}}){
    my $net = $hash->{connections}{$port};
}

If no option is present, it return the item's property:
leaf_instance leaf_module hierarchical_instance hierarchical_module 


Examples:
#1. Get area of one leaf cell
my $area = get_cell_info("AND2X2", "-area");

#2. Get an attribute of one leaf cell
my $is_iso = get_cell_info("ISOX2", "-attribute", "is_isolation_cell");

get_cells

Get all cells in the current module or sub-modules 

Usage:
my @cells = get_cells($pattern, @options);
$pattern: The pattern matching instance name, '*', 'U*', 'U123' or '/UI_.*_./' 
          It can have path, 'u_clk/*', 'u_abc/u_def/*'
@options:
    -help: Print this information
    -hier: Or -h, do the command hierarchically
    -ref ref_pattern: Get cells that has reference matching ref_pattern, E.G. -ref OAI*
    -type type_pattern: Type_pattern can be 'ff','latch','itiming','cg','not','rom','ram' ... 
                        run 'get_lib_cells -type_info' for all existing type in the current libraries
    -type_match type_pattern: Get cells that have one of the types matches the type_pattern
    -leaf: Only leaf cells
    -new: Only new created ECO instances
    -verbose: To print out reference with instance
    -dotpath: Path delimit is '.' instead of '/'
    -nobackslash: Remove backslash 
    -nonscan: Flops/sync-cells not in scan chain including those scan pins tied off
@cells: Returned array with all instances matched


Examples:
#1. Get all instances in the current module 
my @cells = get_cells('*');

#2. Get all instances in the current module 
my @cells = get_cells();

#3. Get all instances matching 'U234*' in the current module
my @cells = get_cells('U234*');

#4. Regular expression. Get all instances starting with U and followed by 
#    two characters, like U10, U99
my @cells = get_cells('/U../');   

#5. Get all instances matching *reg_*_ hierarchically
my @cells = get_cells('*reg_*_', '-hier');

#6. Get all instances hierarchically and having reference matching DFF*
my @cells = get_cells('*', '-hier', '-ref', 'DFF*');

#7. Get all instances in 'u_kb'
my @cells = get_cells('u_kb/*');

#8. Get all flops, sync-cells not in scan chain 
my @cells = get_cells('-hier', '-nonscan');

get_conns

Get connections of net or pin in the top level module, return the leafs and the hierarchical connections 

Usage:
@result = get_conns($net_or_pin, @options);
$net_or_pin: The net name or pin name that needs to get connections.
@options:
   -driver: Return driver only
   -load: Return load only
   -count: Return connections count
@result: a two dimension array
          instance, port_name, pin_or_port, load_or_driver, is_it_a_leaf, 
@result = ([instance_0, pin_0, 'pin', 'load', 1],
           ...
          )


Examples:
#1. Net 'n599' has three connections, instance 'U198' is the driver
get_conns("n599");
gte_344 A[14] pin load 0
U198 Y pin driver 1
U94 AN pin load 1

#2. Net 'qcifhbeat' has three connections, it is output port of the current top level module
get_conns("qcifhbeat")
 qcifhbeat port load
U80 A pin load 1
qcifhbeat_reg Q pin driver 1

#3. The argument in inst/pin format
get_conns("U187/A")
U294 A1 pin load 1
U187 A pin load 1
U80 Y pin driver 1

#4. Return connections count
get_conns("U187/A", "-count");
3

get_coord

Get an instance's coordination 

Usage:
my ($x, $y) = get_coord($instance);
$instance: Instance name


Examples:
my ($x, $y) = get_coord("xbar/U1234");
# $x=100, $y=200 in um

get_definition

Get instantiation of instance

Usage:
my $line = get_definition($inst);
$inst: Instance name.
$line: The instantiating line


Examples:
get_definition('U78');
Returns "AND2X1 U78(.A(n1), .B(n2), .Z(n3));"

get_driver

Get the driver of a net or pin 

Usage:
@driver = get_driver($point, @options);
$point: net name or pin name, 'n12345' or 'U12345/A1'
@options:
   -pin: Return in "inst/pin" format, E.G. "state_reg/Q"
         Return an array if '-pin' is not present
   -nonbuf: Trace the drivers until none buffer 
@driver: The driver in array format, if '-pin' is not present.
         If the point is floating, @driver is empty, 
         $driver[0]: Driver instance name. It is empty if the driver is port
         $driver[1]: Driver pin or port name. If the driver is a port, it is the port name
         $driver[2]: Driver type. It is string "pin" or "port" depending on the driver is port or leaf cell
         $driver[3]: Driver phase. It is valid when -nonbuf is present, 
                     indicating if the driver path is inverted
                     0: not inverted 1: inverted              


Note:
1. If '-pin' is present, return a scalar, $driver = get_driver("n12345", "-pin");
2. Use 'get_drivers' if there are multiple drivers, the return data has different structure


Examples:
#1. Get driver of a net
@driver = get_driver("net12345");
@driver has content of ("U1247", "Y", "pin");

#2. port_abc is input port
@driver = get_driver("port_abc"); 
@driver has content of ("", "port_abc", "port");
           
#3. Return in instance/pin format
$driver = get_driver("net12345", "-pin");
$driver has content of "U1247/Y"

get_drivers

Get the drivers of a net or pin 

Usage:
@drivers = get_drivers($point, @options);
$point: net name or pin name, 'n12345' or 'U12345/A1'
@options:
   -nonbuf: Trace the drivers until none buffer 
   -fanend: Fanin endpoints, flops or input ports or blackbox outputs
@drivers: An array of the drivers, if the point is floating, @drivers is empty, 
         if the point has multi-drivers, @drivers has more than one items.
         For each item in @drivers
         Index 0: instance, it is empty if the driver is port
         Index 1: pin or port, if the driver is port, return port
         Index 2: string "pin" or "port" depending on the driver is port or leaf cell
         Index 3: indicating drive path inverted or not
         If 'nonbuf' is present, the last item in @drivers is the non-buffer driver
         So '$nonbuf = pop @drivers' can get the non-buffer driver 

Note:
Use 'get_driver' instead if the net has only one driver and 'nonbuf' option is not used


Examples:
#1. Get drivers of a net
@drivers = get_drivers("net12345");
@drivers has content of (["U1247", "Y", "pin"]);

#2. 'port_abc' is input port
@drivers = get_drivers("port_abc"); 
@drivers has content of (["", "port_abc", "port"]);
   
#3. Buffers in the path
 @drivers = get_drivers("state_reg/CK", "-nonbuf");
 @drivers has content of
  (
    ["buf_inst0", "Y", "pin"],
    ["inv_inst1", "Y", "pin"],
    ["and_inst2", "Y", "pin"]
  )

#4. Fanin endpoints
 @drivers = get_drivers("u_abc/state_reg/D", "-fanend");
 @drivers has content of
  (
    ["u_abc/csg_valid_reg", "Q", "flop"],
    ["pin_in_cs_start", "GOF_PIN_OUT", "port"],
    ["u_mem_top/u_sram_lut", "Q[1]", "blackbox"]
  )

get_instance

Get instance in the top level module

Usage:
my $instance = get_instance($pattern, @options);
$pattern: Match pattern, can have wildcard "*", if it is empty, it is treated as "*"
@options:
    -module: module name to have its instance name found
$instance: Return the first instance matching


Examples:
#1. The fist hierarchical instance matching 'ui_*'.
$instance = get_instance("ui_*");  

#2. Find the instance name of module 'enet_control' 
$instance = get_instance("-module", "enet_control");

get_instances

Get all hierarchical instances in the top level module 

Usage:
my @instances = get_instances($pattern);
$pattern: Match pattern, can have wildcard "*", if it is empty, it is treated as "*"

@instances: Array of the hierarchical instances


Examples:
@instances = get_instances("UI_*"); # Any hierarchical instances with UI_ as prefix.
@instances = get_instances;         # All hierarchical instances.

get_leaf_pin_dir

Get leaf cell pin's direction input/output/inout

Usage:
my $dir = get_leaf_pin_dir("$leaf_name/$pin");
$pin: pin name, E.G.  A or B or Y
$leaf: Leaf cell name, E.G. NAND2X2
$dir: return direction, input/output/inout


Examples:
my $dir = get_leaf_pin_dir("NAND2X2/A");

get_leafs_count

Get all leaf cells name and count in the top level module, return an array 

Usage:
@leaf_count = get_leafs_count;
@leaf_count: Array of leaf name and count
 ( [leaf0, cnt0], [leaf1, cnt1], ...)


Examples:
@leaf_count = get_leafs_count;
foreach my $leaf_point (@leaf_count){
   my $leaf_name = $leaf_point->[0];
   my $count = $leaf_point->[1];
   print "LEAF: $leaf_name has $count cells\n";
}

get_lib_cells

Get leaf gates in libraries 

Usage:
my @cells = get_lib_cells($pattern, @options);
@options:
     -help:            This information
     -char:            All cells characterization
     -type leaf_type:  Get leaf gates matching type. 
                       Leaf_type can be 'ff', 'latch', 'cg', 'buf', 'not', 'and' ...
     -type_info:       List all types in the current loaded libraries
     -verbose:         If $pattern matches only one lib cell, print the cell lib information
$pattern: Library cell name pattern, can have '*'.
@cells: Return array with name matching

get_loads

Get loads of net in the top level module, return the leafs connections 

Usage:
@result = get_loads($net_or_pin, @options);
$net_or_pin: The net name or pin name that needs to get fanouts.
@options:
   -nonbuf: Trace the loads until none buffer 
   -bypbuf: Don't include buffer/inverter in the return array
   -hier: Loads cross hierarchies
   -fanend: Fanout endpoints, flops or ports
@result: A two dimension array. Each item has format of 'instance' and 'pin_name' if
         the load is leaf cell. Or 'port_name' and 'GOF_PIN_IN' 
@result = ([instance_0, pin_0],
           [instance_1, pin_1],
           [port_name, GOF_PIN_IN],
           ...
          )

get_loads_phase

Get loads of net with phase in the top level module, return the non-buffer/inverter leafs connections 

Usage:
@result = get_loads_phase($net_or_pin, @options);
$net_or_pin: The net name or pin name that needs to get fanouts.
@options:
   -help: This information
@result: A two dimension array. Each item has format of 'instance', 'pin_name' and 'phase', if
         the load is leaf cell. Or 'port_name', 'GOF_PIN_IN' and 'phase' 
@result = ([instance_0, leaf_0, pin_0, 0],
           [instance_1, leaf_0, pin_1, 1],
           [port_name,  GOF_CELL_OUTPORT,GOF_PIN_IN, 1],
           ...
          )

get_logic_cone

Get logic cone of nets or pins

Usage:
$result = get_logic_cone(@InstancePinList, @options);
@InstancePinList: Instance/pin and net list. 
$result: 1, the command fails. 0, the command completed successfully
@options:
    -o file_name: Write output to the file. Default logic_cone.v


Examples:
my @InstPin = ('abc_reg/D', 'n12345');
my $ret = get_logic_cone(@InstPin, '-o', 'MyLogicCone.v');
# The logic cone is written out to verilog file 'MyLogicCone.v'

get_modules

Get modules under current module 

Usage:
@modules = get_modules($pattern, @options);
$pattern: Match pattern, can have wildcard "*", if it is empty, it is treated as "*"
@options:
    -help: Print this information
    -hier: Get all modules hierarchically
@modules: Modules list, ("module0", "module1", ...)


Examples:
@modules = get_modules("*TM*");  # Any hierarchical modules with TM in the name.
@modules = get_modules;          # All hierarchical modules.
@modules = get_modules("-hier"); # All hierarchical modules and sub-modules under current module.

get_net_of

Get net name connecting to a pin 

Usage:
my $net = get_net_of($pin);
$pin: The pin of the instance, 'U1234.A1' or 'U1234/A1' 
$net: The net name connecting to the pin

get_nets

Get nets that matching pattern 

Usage:
@nets = get_nets($pattern, @options);
$pattern: The net naming pattern, "*" or empty for all nets
@options:;
   -const0: Get all constant zero nets
   -const1: Get all constant one nets
@nets: returned net array.


Examples:
1#. Get all nets.
@nets = get_nets("*"); 

2#. All nets with 'dbuffer' as prefix 
@nets = get_nets("dbuffer_*"); 

3#. Get constant nets
@nets = get_nets("-const0");

get_path

Get current hierarchical path 

Usage:
$path = get_path();
$path: The current path

get_pins

Get pins of instance or module 

Usage:
@pins = get_pins($name, @options);
$name: The instance or module name, it can be hierarchical or leaf
@options:
    -input: Get input pins
    -output: Get output pins
    -inout: Get inout pins
    -clock: Get clock pin, only valid for sequential cell, flop latch and gated-clock-cell
    -reset: Get reset pin, return "" if it doesn't exist
    -set:   Get set pin, return "" if it doesn't exist
    -data: Get data pins
    -attribute attribute: Get pins with the attribute
    -nextstate_type type: Get pins matching the type 
            which can be 'data', 'load', 'scan_in', 'scan_enable'
            This option is only valid for sequential cell, flop, latch and gated-clock-cell
If no option is present, get all pins
@pins: All pins returned, in 'instance/pin' format


Examples:
#1. Get input pins of a hierarchical instance
my @pins = get_pins("-input", "u_abc/U123");
Result @pins = ("u_abc/U123/A", "u_abc/U123/B")

#2. Get pins of a leaf cell
@pins = get_pins("AND2X2");
Result @pins = ("A","B","Y")

get_ports

Get all ports in the current top level module 

Usage:
@matching_ports = get_ports($pattern, @options);
$pattern: Match pattern, can have wildcard "*". If it is empty, it is treated as "*"
@options:
          -input: Get input ports only
          -output: Get output ports only
          -inout: Get inout ports only
          -bus: Get ports in bus format instead of bit blast. 
                The API returns an array point if this option present
                The item in the array has format of [port, IsBus, MaxIndex, MinIndex]
                if IsBus == 1, MaxIndex is the Max Index of the bus, E.G, 7 if the bus is port_a[7:0]
                if ISBus==0, MaxIndex and MinIndex are not defined
  
If no option is present, get all ports

@matching_ports: Return ports matching the pattern and the option specified in 
                  the current top level module


Examples:
@ports = get_ports("-input", "dsp2mc_*");  # Get input ports with "dsp2mc_" as prefix
@ports = get_ports;                       # Get all ports

get_ref

Get the reference of the instance, return leaf cell name or hierarchical module name 

Usage:
$reference = get_ref($instance);
$instance: Instance name, "U123"
$reference: Return reference name, "NAND2X4"

get_resolved

Resolve the relative path to module and leaf item

Usage:
($module, $leaf) = get_resolved($relative_path);
$relative_path: Relative path, like "u_abc/u_def/U456"
$module: Resolved module name, like "def"
$leaf: Resolved leaf name, like U456


Examples:
my ($module, $leaf) = get_resolved("u_abc/u_def/U456");
$module has value "def"
$leaf has value "U456"

get_roots

Get root designs name

Usage:
my @rootdesigns = get_roots;
@rootdesign: returned root designs name

get_scan_flop

Get scan flop for the non scan flop 

Usage:
my $scanflop = get_scan_flop($nonscanflop);


Examples:
# Get a corresponding scan flop for non scan flop DFFHQX1
my $scanflop = get_scan_flop("DFFHQX1");

get_spare_cells

ECO command. Get spare cells 

Usage:
get_spare_cells($pattern,@options);
$pattern: Spare leaf cell instance pattern, E.G. 'spare_inst*/spare_gate*'
          Extract spare cells from the database with the pattern
          The first half before '/' is hierarchical instance pattern, it is '*' for top level
          The second half after '/' is leaf instance pattern
          It is ignored if -file option is present
@options:
    -o file_name: Write updated spare cell list to the file, 
                  by default, it has name 'spare_cells_scriptname.list'
    -file spare_list_file: Load in spare cell list file instead of extracting from the database
    -gate_array gate_array_naming: Gate Array naming style, like 'G*', most standard libraries have Gate Array cells naming starting with 'G'
                  This option enables Metal Only Gate Array Spare Cells ECO flow
    -gate_array_filler gate_array_filler_naming: Gate Array Filler naming style, like 'GFILL*',
                  or 'GFILL*|GDCAP*' to include both GA Filler and GA DCAP
    -ignore_load: By default, if the spare cell has fanout, it won't be added into the list. When this option is set, 
                  any matched spare cell is added into the list 
    -exclude_cell_type cell_type: Exclude cell type matching cell_type, cell_type supports wild card like DFFRS*
    -addfreed: Only use deleted gates as spare resource


Examples:
#1. Extract spare cells from the database, matching instances like "SPARE_u0"
get_spare_cells("*/SPARE_*");   

#2. Matching hierarchical instance "someSpare_*" and leaf instance "spr_gate*"
get_spare_cells("someSpare_*/spr_gate*"); 

#3. Extract spare cells from file "spare_cells_list.txt"
get_spare_cells("-file", "spare_cells_list.txt"); 

#4. Enable Gate Array Spare Cells Metal Only ECO Flow, map_spare_cells will map to Gate Array Cells only
get_spare_cells("-gate_array", "G*", "-gate_array_filler", "GFILL*|GDCAP*");

#5. Matching hierarchical instance "someSpare_*" and leaf instance "spr_gate*", but excluding DFFRS*
get_spare_cells("someSpare_*/spr_gate*", "-exclude_cell_type", "DFFRS*"); 

#6. Only used freed gated in metal only ECO
del_gate("u_control/the_status_reg"); # Delete the unused flop and its logic cone will be deleted
fix_design;
get_spare_cells("-addfreed");
map_spare_cells;


Note:
The API has to run on top level, 
set_top('most_top_module')
get_spare_cells("someSpare_*/spr_gate*");

get_spare_in_use

Get spare cells used in the ECO 

Usage:
set_spare_in_use();

gexit

Exit the command interactive mode

Usage:
gexit;

gof_version

Print out GOF version

Usage:
gof_version;

gprint

Print the message and save to log file 

Usage:
gprint($info);
$info: The message to be printed.

insert_gate

ECO command. Insert gate into instance pin

Usage:
insert_gate($pin_name, $gate_type, $leaf_cell_name, $connection, $number);
$pin_name: In the format of "instance/pin"
$gate_type: Gate type like buf, not, and2, mux, or, latch and etc
$leaf_cell_name: Leaf cell name with special name like NAND2X4, *X4
$connection: The connection to the new created instance
$number: The new inserted gate number

return an array with $number of the new created instances, default to be one


Note:
This API is mainly for AI automation

is_leaf

Check if a module or instance is leaf cell 

Usage:
my $leaf = is_leaf($name);
$name: The module or instance under check
$leaf: 0, it's a hierarchical module, (Or the module is not defined)
       1, it's leaf cell. Like, NAND4X8

is_pin_masked

Check if an instance pin has been masked in the current constraint 

Usage:
my $is_masked = is_pin_masked($inst_pin);
$inst_pin: Instance pin, for instance u_control/u_mbist/U1/A
$is_masked: 0, it is not masked
            1, it is masked


Examples:
#1. Check if a DFT MUX has B pin masked in DFT mode 'MX2X4 uMUXD9(.A(ana_in),.B(test_in),.S(atpg_mode),.Z(mux_out9));
set_pin_constant('atpg_mode', 1);
my $is_masked = is_pin_masked("uMUXD9/A"); # It returns 1

is_scan_flop

Check if an instance is scan flop 

Usage:
my $isscan = is_scan_flop($name);
$name: The cell name or instance name
$isscan: 0, it's not a scan flop
         1, it's a scan flop

is_seq

Check if an instance or a leaf cell is a specific sequential cell 

Usage:
my $isseq = is_seq($name, @options);
$name: The instance under check
@options:
    -help:  This information
    -ff:    Check if it's a flipflop
    -bank:  Check if it's a multibit flop
    -latch: Check if it's a latch
    -cg:    Check if it's a gated clock
    -rom:   Check if it's a rom
    -ram:   Check if it's a ram
$isseq: 0, it is not the specific sequential cell
        1, it is the specific sequential cell

list_wireload

Timing command. List all wireload defined in the liberty files

Usage:
list_wireload;

map_spare_cells

ECO command. Map all new created cells to spare cells 

Usage:
$status = map_spare_cells;
$status: 0: the mapping is successful
         non zero: the mapping fails 
@options:
    -help: Print this information.
    -syn Synthesis_command_line: 
            By default, the built-in Synthesis Engine is used.
            External Synthesis tool can be picked by this option
            RTL Compiler and Design Compiler are supported. 
            E.G. "map_spare_cells('-syn', 'rc')" to pick RTL compiler
                 "map_spare_cells('-syn', 'dc_shell')" to pick Design Compiler 
            User can specify more values in the synthesis command
            E.G. '-rc', "rc -E -use_lic RTL_Compiler_Physical"
    -lib_header file_name: This option is Valid when '-syn' option is present. To insert the content of 
                           file 'file_name' to the header of synthesis tcl script. So that '.lib' file to
                           '.db' conversion can be avoided in Design Compiler case. 
                           For example, in Design Compiler case, the file content should have
                             set_search_path [list /project/lib/synopsys_db]
                             set_target_library [list art40_hvt art40_svt]
                             set link_library [list art40_hvt art40_svt]
    -nofreed: Don't add freed gates for synthesis. 
    -nobuf: Don't insert buffers/repeaters in long wires. 
    -notielow: Don't tie low of the input pins of output floating gates, delete them instead
    -pause: Pause the tool before apply the patch
    -exact: Map to the exact name of spare cell, by default the tool picks up a spare cell with 
            the same function, for example, pick up 'INVX2' for 'INVX4'
    -gcmp: Use GOF compiler
    -nospare_mapping: Don't map to physical spare gates even DEF file is loaded

Note:
A DEF file is needed for mapping to exact spare instances.


Examples:
#1. Map to spare cells and use the built-in Synthesis Engine
my $status = map_spare_cells;

#2. Use extra 'rc' option
map_spare_cells('-syn', "rc -E -use_lic RTL_Compiler_Physical")

#3. Don't add freed cells for synthesis
map_spare_cells('-syn', "rc -E -use_lic RTL_Compiler_Physical", "-nofreed")

new_gate

ECO command. Create new gate

Usage:
@return = new_gate($new_net, $reference, $new_instance, $connections);

Note:
if the command is called in the context of return a scalar, the new created instance name
        returns. 
      The usage is the same as new_net, except $reference has to be defined, 
        and return back instance if scalar present.
      Run "help new_net" for detail in the shell "GOF >"

new_net

ECO command. Create a new net

Usage:
@return = new_net($new_net, $reference, $new_instance, $connections);
$new_net: The new net to be created, if not defined, the tool assigns one automatically
$reference: The leaf gate name to drive the net.
$new_instance: The instance name of the new cell, or leave it empty to get automatically assigned.
$connections: The new gate input pins connections 
   Supported formats, 1. Detail format:  ".A(net0),.B(net1),.C(net2)"
                      2. Simple format: Connect to the pins in alphabetical sequence 
                          "net1,net0,net2" indicating .A(net1),.B(net0),.C(net2)
                      3. Mixed format: "instance/pin" and net, "U408/Y,U409/Y,net2" indicating 
                          A to U408/Y, B to U409/Y and C to net2
                      4. The "instance/pin" can have sub-instance hierarchy, "u_abc/U408/Y"
@return: Have the new created instance and net name.
$return[0] : New created instance.
$return[1] : New created net.


Note:
Hierarchical path is supported in any net or instance in the command, 
         for instance, new_net('u_abc/net124', ...
      If the command is called in the context of return a scalar, the new created net name is returned. 
      The new net is assumed to be driven in the path it is created, 
         for instance, new_net('u_abc/eco12345_net124');
      eco12345_net124 should be driven in sub-instance u_abc after it is created.


Examples:
#1. NAND2x2 instance name 'U_eco_123' driving new net 'net123'
new_net("net123", "NAND2X2", "U_eco_123", ".A(n200),.B(n201)");  

#2. INVX2 with instance name 'U_inv' is created in u_abc sub-instance
#  and the input pin of the new invert is driven by n200 in current top level
#  port would be created if n200 doesn't drive input port to u_abc
new_net("u_abc/net123", "INVX2", "u_abc/U_inv", "n200"); 

#3. Create a new net "net500"
new_net("net500");  
 
#4. Create a new instance with new net tied to output pin, input pin is floating.
# $return[0] is new created instance, $return[1] is new created net.
@return = new_net("", "INVX2", "", "");

new_port

ECO command. Create a new port for the current top level module

Usage:
new_port($name, @options);
$name: Port name
@options:
    -input: New an input port
    -output: New an output port
    -inout: New an inout port


Note:
The port name has to be pure words or with bus bit, like, abc[0], abc[1]


Examples:
new_port('prop_control_en', '-input');  # create an input port naming 'prop_control_en'
new_port('prop_state[2]', '-output');   # create an output port with bus bit 'prop_state[2]'
new_port('prop_state[3]', '-output');   # create an output port with bus bit 'prop_state[3]'

place_gate

ECO command. Place an instance to a specific position

Usage:
place_gate($inst, $x, $y);
$inst: The instance to be placed
$x,$y: The coordinate


Note:
This command affects the spare gate mapping of the instance.


Examples:
# A flop is added and placed in some location
# In 'map_spare_cells' command, the flop is mapped to a spare flop closest to the location
change_pin("U123/A", "DFFX1", "eco_dff_reg", ".D(-),.CK(clock)");
place_gate("eco_dff_reg", 100, 200); # location, 100um, 200um
map_spare_cells;

place_port

ECO command. Place port position

Usage:
place_port($port, $x, $y);
$port: The port to be placed
$x,$y: The coordinate
This command has effect on change_port ECO command

pop_top

Pop out the saved top level module from the stack and discard the current setting 

Usage:
pop_top;

post_recovery

ECO command. recover deleted gates after ECO

Usage:
post_recovery(@options);
@options:
   -inv: Replace INV by NAND/NOR
   -incr: Incremental, preceded by map_spare_cells

preserve_modules

Preserve wires in the modules listed or all modules

Usage:
preserve_modules(@module_list, @options);
@options:
   -all: Preserve wires in all modules

push_top

Set the current top level module and push the previous setting to stack, pop_top can retrieve it 

Usage:
push_top($module);
$module: Set the $module as the top level module, push the previous setting to the stack

read_def

Read DEF file

Usage:
my $status = read_def(@files, @options);
@files:  DEF files
@options:
   -defverbose: Report all DEF parsing warnings and errors
$status: If zero, the files have been read in successfully
         if non-zero, failed to read in the files


Examples:
my $status = read_def("soc_top.def");  # Read in soc_top.def 
my $status = read_def("soc_top1.def", "soc_top2.def");  # Multiple DEF files

read_design

Read verilog netlist files 

Usage:
my $top_module = read_design(@files, @options);
@files: Verilog netlist files
@options:
    -imp: The netlists are for the Implementation which are under ECO
    -ref: The netlists are for the Reference
    -prelayout: The netlists are prelayout for hierarchical ports phase detection
    -Top_1: Read design to create Top_1 tree database
    -Top_2: Read design to create Top_2 tree database

Note:
If no -imp or -ref option is provided, the netlist is assumed 'implementation'
$top_module: Return top level module name after the successful read 



Examples:
#1. Read in an implementation netlist file
my $top_module = read_design("-imp", "soc_design_resynthesized.gv");

#2. Read in a reference netlist file
my $top_module = read_design("-ref", "soc_design_released.gv");

#3. Read in two reference netlist files
my $top_module = read_design("-ref", "soc_design_released.gv", "soc_io.gv");

read_file

Read timing violation report file

Usage:
my $status = read_file($file_name, @options);
$file_name: file name
@options:
    -format format: accu/pt
                    accu --- Accucore report file. 
                    pt   --- Prime Time report file
$status: If zero, the file is read in successfully
         if one, failed to read in the file



Note:
Prime Time timing report file should be generated by report_timing command with these options
      report_timing -nosplit -path_type full_clock_expanded -delay max/min -input_pins \
                    -nets -max_paths 10000 -transition_time -capacitance


Examples:
my $status = read_file("soc_primetime_hold.report", "-format", "pt");

read_lef

Read LEF file

Usage:
my $status = read_lef(@files);
@files:  LEF files
$status: If zero, the files are read in successfully
         if one, failed to read in the files


Examples:
my $status = read_lef("soc_top.lef");  # Read in soc_top.lef 
my $status = read_lef("soc_top.lef", "soc_top1.lef", "soc_top2.lef");  # Read in multiple LEF files

read_library

Read standard library or verilog library files 

Usage:
my $status = read_library(@files, @options);
@options:
   -v: Treat the @files as verilog library files
   -lib: Treat the @files as standard library files
   -f library_list_file: Load library files from list file, the list file has format of
                         -v verilog_lib0.v
                         -v verilog_lib1.v
                         -lib tsmc40.lib
   -vmacro: Treat the @files as macro library files which are used as macro cell in ECO
   -rtl: Treat as RTL format
   -gate: Treat as gate format, if not specify -rtl or -gate, the tool automatic picks one
   -top top_module: Only process the module top_module as the leaf cell, discard all other modules
   -ref: The library is for the Reference Netlist only
@files: Standard library files, or verilog library files


Note:
The three options, '-v' '-lib' and '-vmacro' don't coexist.
      If the file has .lib extension, '-lib' can be omitted, and it is treated as standard library file.
      If the file has .v or .vlib extension, '-v' can be omitted, and it is treated as verilog file.
$status: If zero, the file is read in successfully
         if one, failed to read in the file


Examples:
my $status = read_library("arm_40_hvt.lib", "arm_40_io.lib");
my $status = read_library("analog_stub.v", "analog_stub2.vlib");
my $status = read_library("-v", "analog_stub.gv");
my $status = read_library("-vmacro", "macrocell.v");
my $status = read_library("-f", "lib_files.list");
my $status = read_library("-top", "abs_control_top", "abs_control_top_post.v");
my $status = read_library("ref_special.lib", "-ref"); # The library is only for the Reference Netlist

read_rtl

Read RTL files
Support SystemVerilog (IEEE 1800-2017)

Usage:
read_rtl(@files, @options);
@options:
    -imp: The RTL files are for Implementation
    -ref: The RTL files are for Reference


Note:
It can only run on Centos7 and above, Centos6 is not supported.

read_rtlpatch

Read RTL Patch file 

Usage:
my $status = read_rtlpatch($file, @options);
$file: RTL file for ECO 
$status: If zero, the file is read in successfully
         if one, failed in reading the file


Examples:
#1. Read in RTL Patch verilog file
my $status = read_rtlpatch("rtlpatch_change.v");

#2. Multiple RTL Patch files are read in one by one
my $status1 = read_rtlpatch("rtlpatch_change1.v");
my $status2 = read_rtlpatch("rtlpatch_change2.v");

read_sdf

Read SDF Standard Delay Format file 

Usage:
my $status = read_sdf(@options, @files);
@files: SDF files, can be in gzip format

$status: If zero, the files have been read in successfully
         if non-zero, failed to read in the files


Examples:
#1. Read in slow corner top level SDF file for design TM_QCIF
read_sdf("TM_QCIF_slow.sdf.gz");

read_sub_module_netlist

Read in new synthesized netlist file

Usage:
read_sub_module_netlist($sub_module_file, @options);
$sub_module_file: Netlist file name
@options:
    -sub_only: The netlist is one module file, it may have sub-instances as black boxes
    -module module_name: The sub-module name in the original top netlist to be replaced
    -syn_module syn_module_name: The sub-module name in the new synthesized netlist
    -suffix suffix_name: Add suffix string to all modules in the module_name defined in 'module' option


Examples:
#1. Reads in mem_controller module and its sub-modules, ahb_arb module and its sub-modules, and mem_ahb_top module only

read_sub_module_netlist("new_mem_controller.gv", "-module", "mem_controller");
read_sub_module_netlist("new_ahb_arb.gv", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_ahb_top.v", "-module", "mem_ahb_top", "-sub_only");

#2. Reads in new synthesized netlist files, new_mem_controller.gv and new_ahb_arb.gv, and modified parent module new_mem_ahb_top.v.
    The new sub-module netlist new_mem_controller.gv is to replace two uniquified modules in the original top netlist,
    mem_controller_1 and mem_controller_2 and their hierarchical sub-modules.
    The new sub-module netlist new_ahb_arg.gv is to replace ahb_arb and its hierarchical sub-modules in the original top netlist. 
    And the new modified new_mem_ahb_top.v is to replace the sub-parent module mem_ahb_top only.

read_sub_module_netlist("new_mem_controller.gv", "-module", "mem_controller_1", "-syn_module", "mem_controller", "-suffix", "_1");
read_sub_module_netlist("new_mem_controller.gv", "-module", "mem_controller_2", "-syn_module", "mem_controller", "-suffix", "_2");
read_sub_module_netlist("new_ahb_arb.gv", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_ahb_top.v", "-module", "mem_ahb_top", "-sub_only");

read_sub_module_svf

Read in new synthesized design SVF file

Usage:
read_sub_module_svf($sub_module_svf, @options);
$sub_module_svf: Sub-module SVF file name
@options:
    -module module_name: The sub-module name in the original top netlist that will be replaced
    -syn_module syn_module_name: The sub-module name in the new synthesized netlist
    -suffix suffix_string: Add suffix to all modules under the module_name defined by 'module' option, s
Notes: The command can be run several times


Examples:
#1. Reads in mem_controller module and its sub-modules, ahb_arb module and its sub-modules SVF files
read_sub_module_svf("new_mem_controller.svf", "-module", "mem_controller_1", "-syn_module", "mem_controller");
read_sub_module_svf("new_ahb_arb.svf", "-module", "ahb_arb");

read_svf

Read Synopsys SVF text files 

Usage:
my $status = read_svf(@options, @files);
@files: SVF text files
@options:
    -imp: The SVF file is for the Implementation netlist
    -ref: The SVF file is for the Reference Netlist
    -Top_1: The SVF file is for Top_1 tree database
    -Top_2: The SVF file is for Top_2 tree database

$status: If zero, the files have been read in successfully
         if non-zero, failed to read in the files


Note:
This command must be run before read_design 
      SVF should be in text format


Examples:
#1. Read in both SVF files for IMP/REF
read_svf("-ref", "ref_design.svf.txt");
read_svf("-imp", "imp_design.svf.txt");
read_design("-ref", "ref_design.v");
read_design("-imp", "imp_design.v");

read_vcd

Read VCD file

Usage:
read_vcd($vcd_file);
$vcd_file: VCD file name to be read in


Examples:
#1. Read in VCD generated in verify_faults
read_vcd("fault_seu.vcd");

rename_net

ECO command. Rename a net name

Usage:
rename_net($oldname, $newname);
$oldname: Old net name
$newname: New net name

replace_sub_module_netlist

Replace sub-module in the design by a new re-synthesized sub-module netlist and write to a new top netlist

Usage:
replace_sub_module_netlist($new_top_netlist_file);
$new_top_netlist_file: The replaced and new top level full netlist to be written out


Examples:
#1. Replace sub-module 'mem_controller', 'ahb_arb' hierarchically, and 'mem_ahb_top' module, and write out to a new full netlist
read_library("tsmc.lib");
read_design("-imp", "top_ref.gv");
read_sub_module_netlist("new_mem_controller.gv", "-module", "mem_controller");
read_sub_module_netlist("new_ahb_arb.gv", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_ahb_top.v", "-module", "mem_ahb_top", "-sub_only");
replace_sub_module_netlist("new_top_ref.gv");


#2. Replace sub-module 'mem_controller', 'ahb_arb' hierarchically in netlist and SVF, replace 'mem_ahb_top' module only,
    and write out to a new full SVF file and a new netlist

read_library("tsmc.lib");
read_svf("-imp", "top_ref.svf");
read_design("-imp", "top_ref.gv");
read_sub_module_svf("new_mem_controller.svf", "-module", "mem_controller");
read_sub_module_svf("new_ahb_arb.svf", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_controller.gv", "-module", "mem_controller");
read_sub_module_netlist("new_ahb_arb.gv", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_ahb_top.v", "-module", "mem_ahb_top", "-sub_only"); # This module is parent module with instantiation only

replace_sub_module_netlist("new_top_ref.gv"); # Run netlist replacement first 
replace_sub_module_svf("new_top_ref.svf");    # Then SVF replacement

replace_sub_module_svf

Replace sub-module SVF in the design by a new re-synthesized sub-module SVF file content

Usage:
replace_sub_module_svf($new_top_design_svf);
$new_top_design_svf: The replaced and new top level full SVF file to be written out


Examples:
#1. Replace sub-module 'mem_controller', 'ahb_arb' hierarchically in netlist and SVF, replace 'mem_ahb_top' module only,
    and write out to a new full SVF file and a new netlist

read_library("tsmc.lib");
read_svf("-imp", "top_ref.svf");
read_design("-imp", "top_ref.gv");
read_sub_module_svf("new_mem_controller.svf", "-module", "mem_controller");
read_sub_module_svf("new_ahb_arb.svf", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_controller.gv", "-module", "mem_controller");
read_sub_module_netlist("new_ahb_arb.gv", "-module", "ahb_arb");
read_sub_module_netlist("new_mem_ahb_top.v", "-module", "mem_ahb_top", "-sub_only"); # This module is parent module with instantiation only

replace_sub_module_netlist("new_top_ref.gv"); # Run netlist replacement first 
replace_sub_module_svf("new_top_ref.svf");    # Then SVF replacement

report_eco

Report ECO

Usage:
report_eco($filename, @options);
$filename: Write report to the file name. If $filename is not present, print to screen
@options:
    -help: Print this information
    -simple: Print in simple format

report_spares

Report Spare cells

Usage:
report_spares;

report_timing

Timing command. Report timing

Usage:
report_timing(@options);
@options:
    -help: Prints this information
    -delay_type $delay_type: Specifies the type of path delay: max (default) or min
    -from: $startpoint, Starting point of the timing report
    -to:   $endpoint, Ending point of the timing report
    -through: $through_points, Through points, the value can be an array point
    -thr_and: Through points should all present 
    -max_paths number: Max path number to report, if it is not set, only report one path
    -all: Reports all timing paths
    -input_pins: Displays input pins of instances
    -nosplit: Prevents line splitting

Note:
If none of the 'from' or 'to' or 'through' option is present, the timing report is on the paths that go through the ECO instances


Examples:
#1. Report timing on the paths that go through the ECO instances
report_timing();

#2. Report timing on the instances that in through option
my $thr_instances = ["u_control/u_clk/U120", "u_control/u_mbist/U117"];
report_timing("-through", $thr_instances);

#3. Report timing on the instances that in through option and they should all appear in the report path
my $thr_instances = ["u_control/u_clk/U120", "u_control/u_mbist/U117"];
report_timing("-through", $thr_instances, "-thr_and");

restore_session

Restore ECO session

Usage:
restore_session("$directory/$session_name");
$directory: The directory that the session has been saved
$session_name: The session name


Examples:
# To restore the session "myeco" in sub-directory "mach_ai"
restore_session("mach_ai/myeco");

rtl_compare

RTL to RTL compare
The compare result is used in fix_design, so that Gate to Gate comparing can be skipped

Usage:
rtl_compare(@options);
@options:

run

Run Netlist processing script

Usage:
run($script_name);


Examples:
run("eco2.pl");

run_lec

Run Logic Equivalence Check of the Implementation Netlist vs the Reference Netlist 

Usage:
run_lec(@options);
@options:
    -list_file the_list_file: The LEC point list file 
             The list file format:
                inst: u_def/u_sdef/state_reg_1_
                pin:  u_control/u_sreg/u_mem_128x24/A[0]
                port: PORT_READY_OUT

run_nl

AI command, run natural language command

Usage:
run_nl("Insert X12 invert into u_abc/u_def/U123 A pin");

Note:
1. Make sure AI server is running in local
2. Enable AI by set_ai(1)

save_session

Save ECO session

Usage:
save_session("$directory/$session_name");
$directory: The directory that the session should be saved
$session_name: The session name


Examples:
# To save a session "my_eco" in sub-directory "mach_ai"
save_session("mach_ai/my_eco");

sch

Launch schematic to verify ECO

Usage:
sch(@instances, @options);
@instances: Instances or nets in the current module to be displayed on the schematic
@options:
    -set value: Set a value when launch the schematic
    -to value: To existing schematic
    -both: Load the item in both implementation and reference netlist


Examples:
sch("U123", "U456", "inst0");
sch("clk")
sch("in1", "-set", "1");
sch("in1", "-to", "1"); # No action if schematic 1 doesn't exist

set_ai

Enable/disable AI. A local AI server should be running

Usage:
set_ai($on_off);
$on_off: Default 0
         0, Disable AI
         1: Enable AI

set_auto_fix_floating

ECO setting. Enable automatic fixing floating input ports after fix_modules
By default, it is enabled.

Usage:
set_auto_fix_floating(0);  --- Disable automatic fixing floating input ports.

set_bfix

Enable or disable BFIX features which is for precise combinational logic fix  

Usage:
set_bfix($val);
$val: Default 0x3
      Bit 0, Set one to enable Reorder Method
      Bit 1, Set one to enable Cutpoint Method
      bit 2, Set one to force using Reorder/Cutpoint Method instead of Structure Method


Note:
It should run before fix_design

set_blackbox

Set Blackbox on Modules

Usage:
set_blackbox(@modules, @options);
@module: Module names to be set as blackbox, accept wild card '*'
@options:
   -hier: Set blackbox on the module and its sub-hierarchical modules
          Only valid on module name without '*'


Note:
This command can be used multiple times


Examples:
#1. Set Blackbox on DW modules
set_blackbox("*DW_pipe*");

#2. Set Blackbox on 'ABC' and 'DEF' modules
set_blackbox("ABC", "DEF");

#3. Set Blackbox on memory_control and its sub-hierarchical modules. Set Blackbox on one DW as well
set_blackbox("memory_control", "-hier");
set_blackbox("DW_adder_123");

set_bound_opti

Set boundary optimization checking 

Usage:
set_bound_opti($val);
$val: 0, disable boundary optimization checking
      1, enable boundary optimization checking (default)

set_buffer

Set buffer type. The tool automatically picks one if the command is not called 

Usage:
set_buffer($buffer);
$buffer: Lib cell name for buffer


Examples:
set_buffer("BUFX2");

set_buffer_distance

Set distance limit for inserting buffer

Usage:
set_buffer_distance($distance_val);
$distance_val: distance to insert buffer, in um

set_clock_uncertainty

Timing command. Set clock uncertainty

Usage:
set_clock_uncertainty($value);
$value: Uncertainty value

set_cluster_command

Set cluster command in parallel fault verification

Usage:
set_cluster_command($cluster_command);
$cluster_command: Command to submit jobs to cluster computers


Examples:
#1. Set cluster command 
set_cluster_command("bsub_lsf -queue");

set_cluster_timeout

Set time out for cluster command

Usage:
set_cluster_timeout($time_in_seconds);
$time_in_seconds: An integer number in seconds


Note:
cluster time out number should be large than solver time out


Examples:
#1. Set solver time out to ~12 hours
set_cluster_timeout(43200);

set_constraints

Set constraints for map_spare_cells command

Usage:
set_constraints(@options);
@options:;
   -type type_constraint : Set spare cell type constraint, type_constraint is a string 
                           listing spare cells separated by ',', get_spare_cells should not be used if -type is present
   -num num_constraint   : Set spare cell number constraint, num_constraint is a string 
                           in the format of 'mux<16,nand<18'
   -type_limit limit_string : Set cell type limit to be less than a number, for example A9TR type less than 10, 'A9TR<10'
                             All constraints is separated by ',' in the format of 'X8B<9,X0P5A<1'

Note:
The number constraint only controls the number of spare types to be used. The spare gates list should have 
      'nand/and', 'nor/or' and 'inv' types of leaf cells for synthesis mapping, and have spare flops for direct mapping, 'mux' is optional. 
      If used with get_spare_cells command, this command should be used after get_spare_cells, check example #3 


Examples:
#1. Use less than 16 'mux' and less than 18 'nand' spare gates in map_spare_cells
get_spare_cells("u_Spare*/*spr_gate*");
set_constraints('-num', 'mux<16,nand<18');
map_spare_cells;


#2. Use NAD2X1 NOR2X1 INVX1 and MUX2X1 as spare type gates
set_constraints('-type', 'NAND2X1,NOR2X1,INVX1,MUX2X1');
map_spare_cells;

#3. Set constraint after spare list created 
get_spare_cells("u_Spare*/*spr_gate*");
set_constraints('-num', 'and<1'); # So that no AND spare gate will be used
map_spare_cells;

#4. Set type limit after spare list created
get_spare_cells("u_Spare*/*spr_gate*");
set_constraints('-type_limit', 'ULVT<5,ELVT<6'); 
map_spare_cells;

set_cutpoint_thresh

Set Cutpoint Threshold

Usage:
set_cutpoint_thresh($val);
$val: Threshold value, default 100

set_cutpoint_ultra

Set the level in doing CutPoint Ultra 

Usage:
set_cutpoint_ultra($val);
$val: 0, Disable cutpoint ultra
      1, Enable cutpoint ultra (default)

set_define

Set define 

Usage:
set_define($define, $value, @options);
@options:
    -imp: The define is for Implementation only
    -ref: The define is for Reference only
$define: The define item
$value: The value, optional


Examples:
#1. Set define SYNTHESIS for both netlists
set_define("SYNTHESIS");

#2. Set define NO_DFT_LOGIC for Reference only
set_define("NO_DFT_LOGIC", "-ref");

#3. Set define SIMULATION to 0
set_define("SIMULATION", 0);

set_detect_points

set detect points

Usage:
set_detect_points(@points, @options);
@points: Detect points 
@options:
   -help: Print this info


Note:
The command can be run multiple times


Examples:
#1. Set data_error_ml as detect points
set_detect_points("data_error_ml");

#2. Set data_error_ml and u_cpu/err_det_reg as detect points
set_detect_points("data_error_ml");
set_detect_points("u_cpu/err_det_reg");

set_disable_cross_hierarchy_merge

Set this variable to disable cross hierarchy register merging

Usage:
set_disable_cross_hierarchy_merge($value);
$value: 0, disable
        1, enable. Default

set_disable_lib_cache

Disable liberty file cache

Usage:
set_disable_lib_cache($value);
$value: 0, enable liberty file cache (default)
        1, disable liberty file cache

set_dont_fix_modules

Set dont fix property on modules

Usage:
set_dont_fix_modules(@modules);
@module: Module names not to be fixed

Example:

#1. Set dont fix on pcie_ctrl and pcie_top module
set_dont_fix_modules("pcie_ctrl", "pcie_top");

set_dont_use

Set dont use property on library cells

Usage:
set_dont_use(@cell_list);
@cell_list: List of the dont use cells which is not used in automatic ECO. Wild card '*' is supported


Note:
If the command is used multiple times, the latest command overrides the previous ones


Examples:
#1. Don't use these two cells
set_dont_use("INVX30","AND2X24");

#2. Don't use power cell matching PWR_
set_dont_use("PWR_*");

#2. If run two times, the second one has effect, set dont use on "CINV_*"
set_dont_use("SINV_*");
set_dont_use("CINV_*");

set_eco_effort

ECO setting. Set ECO effort

Usage:
set_eco_effort($effort);
$effort: One of the three choices, high, medium and low. By default, high effort is used


Examples:
#1. Change ECO effort to medium
set_eco_effort("medium");

set_eco_point_json

Set a JSON file name for saving the ECO point data. 
The JSON file can be applied to another netlist ECO, so that the full LEC has no need to be rerun

Usage:
set_eco_point_json($json_name);
$json_name: The JSON file name


Note:
This command should be run before fix_design

set_equal

ECO setting. Set two points to be equivalent in the Reference and Implementation Netlists
             The points can be input port, flop instance or output pin of black-box.
             The point names should have 'i:' or 'r:' as prefix to indicate they are for the Reference or Implementation, or
             the first point is assumed as Reference and the second Implementation.
             Both of the points can be from Reference or Implementation

Usage:
set_equal($ref_point, $imp_point);
$ref_point: The point in the Reference Netlist. It should be the first argument if it doesn't have 'i:' or 'r:' as prefix
$imp_point: The point in the Implementation Netlist. It should be the second argument if it doesn't have 'i:' or 'r:' as prefix


Examples:
#1. Input port 'in_a' in Reference Netlist is equivalent to input port 'in_b' in Implementation Netlist in top module
set_top('top_module');
set_equal('r:in_a', 'i:in_b');
 
#2. Flop instance 'subinst/flopa_reg' is equivalent to input port 'IN0' in the Implementation Netlist
set_top('top_module');
set_equal('i:subinst/flopa_reg', 'i:IN0');
fix_design();

set_error_out

Set error out setting

Usage:
set_error_out($value);
$value: 1, Abort the program when APIs have run error, default setting
        0, Ignore the error and continue the program


Examples:
# Program continues when there is error in change_pin
set_error_out(0);
change_pin("nonexisting_instance/A", "1'b0"); # It will continue, even though nonexisting_instance is not in the database

set_exit_on_error

Whether the tool should exit when the script runs into an error

Usage:
set_exit_on_error($error, $bit);
$error: Error pattern, wild card support. 'E-001', 'E-*'
$bit: 1, Exit on the error, default
      0, Don't exit on the error

set_exit_on_warning

Whether the tool should exit when the script runs into a warning

Usage:
set_exit_on_warning($warning, $bit);
$warning: Warning pattern, wild card support. 'W-001', 'W-*'
$bit: 1, Exit on the warning
      0, Don't exit on the warning, default

set_false_path

Timing command. Set false path

Usage:
set_false_path(@options);
@options:
    -help: Print this information
    -from: $startpoint, set false path on the starting point
    -to:   $endpoint, set false path on the ending point
    -through: $through_point, set false path on the through point


Examples:
#1. Set false path on u_control/u_subsm/state_reg_* as from points
set_false_path("-from", "u_control/u_subsm/state_reg_*");

set_floating_as_zero

Set floating net as constant zero 

Usage:
set_floating_as_zero($value);
$value: 0, disable floating net as constant zero
        1, enable floating net as constant zero (default)

set_flop_default_eco

Set flop default eco by inverting input pin and output pin

Usage:
set_flop_default_eco($value);
$value: 1 to enable flop default eco by inverting input pin and output pin

set_flop_merge_enable

Inside module flop merge enable

Usage:
set_flop_merge_enable($setting,@options);
$setting: 0, disable inside module flop merge 
          1, enable inside module flop merge (default)

set_high_effort

Set high ECO effort on modules 

Usage:
set_high_effort(@options);
@options:
    -help: Print this information
    -include module_list: Only set high ECO effort on the modules listed,
                         module_list has format of module names separated by ',', wild card is acceptable
                         For example, 'mem_control,dma_*'
    -exclude module_list: Exclude high ECO effort on the modules listed
                         module_list has format of module names separated by ',', wild card is acceptable
                         For example, 'mem_control,dma_*'
    -timeout time_in_seconds: Set time out for each run, default to time out in 900 seconds
                         time_in_seconds is an integer indicating time out in seconds


Examples:
#1. Set ECO high effort on all modules under ECO
set_high_effort();

#2. Set ECO high effort on module 'mem_control_1'
set_high_effort('-include', 'mem_control_1');

#3. Set ECO high effort on modules matching 'mem_control_*' and modules matching 'dma_*'
set_high_effort('-include', 'mem_control_*,dma_*');

#4. Enable ECO high effort, but excluding module 'mem_control_1  '
set_high_effort('-exclude', 'mem_control_1');

#5. Enable ECO high effort with time out in 600 seconds
set_high_effort('-timeout', 600);

set_ignore_instance

ECO setting. Set ignored sequential or blackbox instances in ECO

Usage:
set_ignore_instnace(@ignored_instances)
@ignored_instances: Instances to be ignored in ECO, accept wild card '*'


Examples:
#1. Ignore instances matching RAND_CNT_reg* in ECO
set_top('VIDEO_TOP');
set_ignore_instance('RAND_CNT_reg*');
set_top('DESIGN_TOP');
fix_design();

#2. Ignore instances matching current_state_reg* in instance u_video
set_top('DESIGN_TOP');
set_ignore_instance('u_video/current_state_reg*');
fix_design();

set_ignore_network

ECO setting. Set ignore network in ECO

Usage:
set_ignore_network(@ignored_nets, @options)
@ignored_nets: Net and its network to be ignored in ECO, accept wild card '*'
@options:
   -help: Print this information
   -pin:  @ignored_nets are in pin format, for example, 'DONT_mux_clk/PIN_Y'


Examples:
#1. Ignore scan_en and scan_in
set_ignore_network('scan_en*', 'scan_in*'); 

#2. Ignore PAD PAD_SCAN_EN's output pin 'core' and its network
set_ignore_network('PAD_SCAN_EN/core', '-pin');

set_ignore_output

ECO setting. Set ignore output ports

Usage:
set_ignore_output(@ignored_ports, @options)
@ignored_ports: Output ports to be ignored, accept wild card '*'
@options:
   -help: Print this information
   -both: Apply to both Reference and Implementation Netlist. Enabled by default
   -ref:  Apply to Reference Netlist
   -imp:  Apply to Implementation Netlist
 

Examples:
#1. Ignore output ports matching *scan_out* in ECO
set_top('design_top');
set_ignore_output('*scan_out*');
set_pin_constant('scan_en', 0);
fix_design();

#2. Ignore output ports matching *TSTCON* in Implementation Netlist
set_top('CHIP_TOP');
set_ignore_output('*TSTCON*', '-imp');

set_ignore_pin

set ignore on the pin of black box like memory in logic equivalence checking 

Usage:
set_ignore_pin("$cell_name/$pin_name");
$cell_name: The black box cell name (Not instance name)
$pin_name: The cell pin name, wildcard is supported, for example "TM*" to match TM[0] TM[1] ...


Examples:
set_ignore_pin("TSMC_MEM_256X29/TCEN");
set_ignore_pin("TSMC_MEM_256X29/TA*");

set_inc_dirs

Set include directories

Usage:
set_inc_dirs(@include_directory_list, @options);
@options:
    -imp: The include directories are for Implementation only
    -ref: The include directories are for Reference only
@include_directory_list: List of all include directories


Examples:
#1. Set include directories for Reference only
set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include", "-ref");

#2. Set include directories for Implementation only
set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include", "-imp");

#3. Set include directories for both
set_inc_dirs("/project/nd900/vlib/include", "/project/nd900/IPS/include");

set_initial_trans

Timing command. Set initial transition for clock

Usage:
set_initial_trans($value);
$value: Transition value

set_input_delay

Timing command. Set input delay

Usage:
set_input_delay($port_name, $delay_value, @options);
@options:
    -clock clock_name: Specifies the clock that relates to the delay
$port_name: Input port name, accept wild card '*'
$delay_value: Delay value in ns


Examples:
#1. Set input port to all APB bus input
set_input_delay("port_apb_*"", 0.1);

set_input_transition

Timing command. Set input transition to all input ports

Usage:
set_input_transition($value);
$value: Transition value

set_inside_mod

Set fix scope inside the current module
If set to 1, the tool only use resource inside the current module to fix the non-eq points.
By default, it is disabled.

Usage:
set_inside_mod($val);
$val: 0, disable 1, enable

set_inst

Set the current instance, alias of 'current_instance'

Usage:
set_inst($instance);
$instance: Set $instance as the current instance.
         If the argument is missing, return the current setting
         ".." set to parent, "~" set to the most top level module 

Note:
It can be reset to the root top module by 'undo_eco'. It has same effect of 'set_top' and 'current_design'

set_inv

ECO setting. Set two points to be inverted in the Reference and Implementation Netlists
             The points can be input port, flop instance or black-box's output pin.
             The point names should have 'i:' or 'r:' as prefix to indicate they are for Reference or Implementation, or
             the first point is assumed as Reference and the second Implementation.
             Both of the points can be from Reference or Implementation by using 'i:' or 'r:' on both point names.

Usage:
set_inv($ref_point, $imp_point);
$ref_point: The point in the Reference Netlist. It should be the first argument if it doesn't have 'i:' or 'r:' as prefix
$imp_point: The point in the Implementation Netlist. It should be the second argument if it doesn't have 'i:' or 'r:' as prefix


Examples:
#1. Input port 'in_a' in the Reference Netlist is inverted to input port 'in_a_BAR' in the Implementation Netlist in top module
set_top('top_module');
set_inv('r:in_a', 'i:in_a_BAR');

set_invert

Set invert type. The tool automatically picks one if the command is not called 

Usage:
set_invert($invert);
$invert: Lib cell name for invert


Examples:
set_invert("INVX2");

set_keep_format

Keep the format of the original verilog when ECO is done (Keep original netlist format)

Usage:
set_keep_format($value);
$value: 0, disable format keeping (default)
        1, enable format keeping.

set_keep_tree

Set keeping buffer tree, so that buffer tree won't be removed in ECO
By default , it is disabled.

Usage:
set_keep_tree($val);
$val: 0, disable 1, enable

set_keypoints_rep_in_ref

ECO setting. Replace keypoints naming in Reference Netlist.
Keypoints naming matching the first argument, and replace the matched string by the second argument

Usage:
set_keypoints_rep_in_ref($match_string, $rep_string);
$match_string: Keypoints naming matching this string
$rep_string: To replace the matched string by this string


Note:
The command only apply to Reference Netlist


Examples:
#1. Replace the last '_' in Keypoints naming in Reference Netlist
set_keypoints_rep_in_ref('_$', '');

#2. Replace the last '0' in Keypoints naming in Reference Netlist
set_keypoints_rep_in_ref('0$', '');

set_leaf

Set a hierarchical module to be leaf. Useful to stub hierarchical instances

Usage:
set_leaf($module_name, $value);
$module_name: The module to be set leaf or not set to leaf
$value: 1 or larger than 1, set the module as leaf. 0 not set to leaf. 
        If $value is not present, the default value is 1.


Examples:
set_leaf($module_a); # set $module_a as a leaf
set_leaf($module_a, 1); # same as the above
set_leaf($module_a, 0); # remove the leaf setting

set_log_file

Set log file name

Usage:
set_log_file($filename);
$filename: Log file name

set_low_effort

Set low ECO effort to speed up ECO process 

Usage:
set_low_effort(@options);
@options:
    -help: Print this information


Examples:
#1. Set ECO low effort on all modules under ECO
set_low_effort();

set_mapped_point

ECO setting. Set two points mapped in Reference and Implementation Netlists

Usage:
set_mapped_point($ref_point, $imp_point, @options);
$ref_point: Register instance or output port in Reference Netlist
$imp_point: Register instance or output port in Implementation Netlist
@options:
    -invert: The two points are expected to be inverted


Examples:
#1. Two outputs are mapped key points
set_mapped_point("ref_sync", "imp_sync");

set_mapping_method

LEC setting. Detecting flop phase inversion.

Usage:
set_mapping_method("-phase");

set_max_lines

Set max output lines

Usage:
set_max_lines($num);
$num: New max lines number. Default to be 500

set_max_loop

Setup max loop, the tool stops logic optimization when max loop number is reached

Usage:
set_max_loop($value);

$value: Setup BDD threshold, default 40000

set_mod2mod

Set reference module mapping to implementation module

Usage:
set_mod2mod($refmod, $impmod);
$refmod: The reference module name
$impmod: The implementation module name

Note:
The command is used when reference netlist is partial

set_mu

MU configuration, setup MU value for BDD threshold

Usage:
set_mu($value);
$value: Setup BDD threshold, default 12000

set_multibit_blasting

Set blasting on multibit flops 
set_multibit_blasting($enable);
$enable: 0, disable multibit flop blasting
         1, enable multibit flop blasting (default)

Note:
This command should run before read_design


Examples:
set_multibit_blasting(1);
read_design("-ref", "ref.v");
read_design("-imp", "imp.v");

set_multibit_output

Set multibit flops output in ECO results 
set_multibit_output($enable);
$enable: 0, disable multibit flops output (default)
         1, enable multibit flops output 


Examples:
set_multibit_output(1);
write_verilog("eco_result.v");

set_net_constant

Set net to a constant value in DFT constraint 

Usage:
set_net_constant($net, $value, @options);
$net: Net name. It can be a bus.
$value: Decimal value that the pin should be set
@options:
    -help: Print this information
    -both: Set the net to the constant value on both Implementation and Reference. Enabled by default.
    -imp:  Set the net to the constant only on Implementation
    -ref:  Set the net to the constant only on Reference


Examples:
#1. Set all_test net to zero in Implementation Netlist
set_top('DESIGN_TOP_DFT_WRAPPER');
set_net_constant('all_test', 0, '-imp');
set_ignore_output('PIN_EDT_CHANNEL_OUT*', '-imp');
fix_design();

set_no_patch_opt

Disable patch optimization

Usage:
set_no_patch_opt($value);
$value: 0, Enable patch optimization in fix_design (default).
        1, Disable patch optimization in fix_design

set_noexact_pin_match

ECO setting. Don't match some special pins
These pins normally don't exist in RTL but added by Synthesis, DFT or other tools.

Usage:
set_noexact_pin_match($pattern);
$pattern: Pin pattern in regular expression, '\bIN\d+\b'


Note:
The command only apply to Reference Netlist. It should be run before reading reference netlist


Examples:
#1. Don't match pins like IN0, IN1, IN2
set_noexact_pin_match('\bIN\d+\b');
read_design('-ref', 'ref_netlist.v');

set_observe_points

set observe points

Usage:
set_observe_points(@points, @options);
@points: Observation points 
@options:
   -help: Print this info
   -comb: The points are input pins of combinational gates


Note:
The command can be run multiple times


Examples:
#1. Set data_out_ml bus as observe points
set_observe_points("data_out_ml*");

#2. Set data_out_ml bus and u_cpu/valid_status_regas observe points
set_observe_points("data_out_ml*");
set_observe_points("u_cpu/valid_status_reg");

set_one_fault

Set one fault for verify_state command

Usage:
set_one_fault($fault_name);
$fault_name: Fault name 


Examples:
#1. Set stuck-at 0 fault to a NAND gate input 
set_one_fault("u_top/u_ctrl/U123/A:SA0");

set_only_use

In optimize_patch, Only use these cells listed 

Usage:
set_only_use(@cell_list);
@cell_list: List of the cells that are used in optimize_patch. Wild card '*' is supported


Examples:
#1. Use these two cells
set_only_use("INVX30","AND2X24");

#2. Use any type of invert and nand gate
set_only_use("INV*", "NAND*");

set_output_delay

Timing command. Set output delay

Usage:
set_output_delay($port_name, $delay_value, @options);
@options:
    -clock clock_name: Specifies the clock that relates to the delay
$port_name: Output port name, accept wild card '*'
$delay_value: Delay value in ns


Examples:
#1. Set output delay to all memory output
set_output_delay("mem_out_*"", 2.1);

set_output_load

Timing command. Set output load to all output ports

Usage:
set_output_load($value);
$value: Output load value

set_phase_adjust_en

Enable phase adjusting 

Usage:
set_phase_adjust_en($val);
$val: 0, disable phase adjusting
      1, enable phase adjusting (default)

set_phase_inv

ECO setting. Set flops invert phase in the Reference and Implementation Netlists

Usage:
set_phase_inv($flop1, $flop2 ...);
$flop1, $flop2: Flop instance list in full path


Examples:
#1. Set flop instance u_ip/u_control/a_reg to have invert phase
set_top('top_module');
set_phase_inv('u_ip/u_control/a_reg');

#2. Set flop instances u_ip/u_control/a_reg and u_ip/u_control_b/b_reg to have invert phase
set_top('top_module');
set_phase_inv('u_ip/u_control/a_reg', 'u_ip/u_control_b/b_reg');

set_physical_aware

Enable physical aware ECO 

Usage:
set_physical_aware($value);
$value: 0, disable physical aware ECO 
        1, enable physical aware ECO (default)

set_pin_constant

Set pin to a constant value in DFT constraint 

Usage:
set_pin_constant($pin, $value, @options);
$pin: Input pin name. It can be a bus, or an instance pin.
$value: Decimal value that the pin should be set
@options:
    -help: Print this information
    -both: Set the pin to the constant value on both Implementation and Reference. Enabled by default.
    -imp:  Set the pin to the constant only on Implementation
    -ref:  Set the pin to the constant only on Reference


Examples:
#1. Set test scan test pin to zero
set_top('DESING_TOP');
set_pin_constant('PIN_SCAN_TEST', 0);
set_ignore_output('PIN_SCAN_SO*');
fix_design();

#2. Set one bus port to all ones on Implementation
set_top('DESING_TOP');
set_pin_constant('PIN_CONTROL[3:0]', 15, '-imp');
fix_design();

set_power

Set power pins connections for leaf cell

Usage:
set_power($leaf_cell, $connections);
$leaf_cell: Leaf cell name. Like NAND2X4
$connections: Power pins connections, like ".GND(GND),.VDD(VDD)"

set_preserve

Set preserve property on instances. The tool does not remove them in ECO 

Usage:
set_preserve(@instances, @options);
@options:
   -hier: Set preserve globally, the specified instances will be preserved in all modules
@instances: Instances to be preserved in the current module
            Accept wild card '*'


Examples:
#1. Preserver two instances in mcu_top 
push_top("mcu_top");
set_preserve("u_donttouch0", "u_1000");
pop_top;

#2. Preserve all DONT* instances in abc_mod
push_top("abc_mod");
set_preserve("DONT*");
pop_top;

#3. Preserve clock_tree_* instance in all modules, push_top/set_top are ignored
set_preserve("clock_tree_*", "-hier");

set_quiet

Run script in quiet mode

Usage:
set_quiet;

set_recovery_distance

Set distance limit for gates recovery in ECO

Usage:
set_recovery_distance($distance);
$distance: Distance to recover deleted gate, in unit of 'um'

set_remove_undsc_in_ref

ECO setting. Remove last '_' in flop instance in Reference Netlist
It's a special command to remove the last '_' in flop instance in Reference Netlist 
   to match Implementation Netlist.

Usage:
set_remove_undsc_in_ref($value);
$value: 1, enable. 0, disable


Note:
The command only apply to Reference Netlist

set_rtl_eco_full_hier_fan

RTL ECO has full hierarchical fanout

Usage:
set_rtl_eco_full_hier_fan($val);
$value: 0, disable full hierarchical fanout (default)
        1, enable full hierarchical fanout

set_save_mapped_instance

Dump key points mapping information for LEC

Usage:
set_save_mapped_instance(1);


Note:
The command should be run before fix_design

Example:

set_save_mapped_instance(1);
fix_design();

set_scan_pairs

Set scan output ports, the command is used with dft_drc

Usage:
set_scan_pairs(@scan_in_out_pairs);
@scan_in_out_pairs: List of pairs of scan in and scan out pins


Note:
The command can run multiple times


Examples:
#1. Set all scan_si[100:0] scan_so[100:0] as scan in/out ports
set_top("THE_DESIGN");
for(my $i=0;$i<=100;$i++){
  set_scan_pairs("scan_si[$i]", "scan_so[$i]");
}
set_top("THE_DFT_TOP"); # THE_DFT_TOP has THE_DESIGN as an instance
dft_drc;

#2. Check DFT DRC on a_scan_si[6]/a_scan_so[6] and b_scan_in[7]/b_scan_out[7]
set_scan_pairs("a_scan_si[6]", "a_scan_so[6]", "b_scan_in[7]", "b_scan_out[7]");
dft_drc;

set_sn_vs_rn

Check set pin and reset pin priority

Usage:
set_sn_vs_rn($val);
$val: 1, Check set/reset pins priority, default
      0, Don't check set/reset pins priority

set_solver_timeout

Set time out for solver

Usage:
set_solver_timeout($time_in_seconds);
$time_in_seconds: An integer number in seconds


Examples:
#1. Set solver time out to ~10 hours
set_solver_timeout(36000);

set_tiehi_net

Set tiehi net name, it is used if tiehi net is needed in ECO 

Usage:
set_tiehi_net($netname);
$netname: Tiehi net name, default to be 1'b1


Note:
If Tie High Cell is preferred, the value should be set to empty
      set_tiehi_net("");

set_tielo_net

Set tielo net name, it is used if tielo net is needed in ECO 

Usage:
set_tielo_net($netname);
$netname: Tielo net name, default to be 1'b0


Note:
If Tie Low Cell is preferred, the value should be set to empty
      set_tielo_net("");


Examples:
set_tielo_net("___logic0___"); 
set_tielo_net("TIE_HILO_TIELO_NET");
set_tielo_net(""); # Use Tie Cell

set_time_frame_limit

GOF Formal only. Set limitation for time frame in fault verification, default 35

Usage:
set_time_frame_limit($frame_number);
$frame_number: An integer number


Examples:
#1. Set time frame limit to 256
set_time_frame_limit(256);

set_top

Set the current top level module 

Usage:
set_top($module);
$module: Set $module as the current top level module.
         If the argument is missing, return the current setting
         ".." set to the parent module, "~" set to the most top level module 

Note:
It can be reset to the root top module by 'undo_eco'

set_top_ref

Set the top level module for the Reference design 
Usage set_top_ref($module);
Notes:
Set top module for the Reference Netlist due to unmatched hierarchy.

set_tree

Set the current tree, if there are more than one sets of databases 

Usage:
set_tree($tree);
$tree: It can be Top, Top_ref, Top_1 or Top_2
       Top: The Implementation Netlist
       Top_ref: The Reference Netlist
       Top_1: The netlist loaded by -Top_1 option
       Top_2: The netlist loaded by -Top_2 option
       If $tree is not defined, the current database name is returned


Note:
Implementation tree 'Top' has aliases of 'imp', 'IMP'
      Reference tree 'Top_ref' has aliases of 'ref', 'REF'


Examples:
set_tree("Top"); # Set to the Implementation Netlist tree
set_tree("Top_ref"); # Set to the Reference Netlist tree
set_tree();  # Return the current database name. E.G. 'Top_ref'

set_user_match

Set match between multi-bit flops to multi-bit flops, and between multi-bit flops to single bit flop

Usage:
set_user_match($inst1, $inst2);
$inst1: The first flop instance, in the format of 'r:reg_1_0A/\*dff.00.0\*' if it is multibit 
           or 'r:reg_1A' if it is single bit
$inst2: The second flop instance, in the format of 'i:reg_1_0A/\*dff.00.0\*' if it is multibit 
           or 'i:reg_1A' if it is single bit


Examples:
set_user_match('r:reg_1_0A/\*dff.00.0\*', 'i:reg_0A');
set_user_match('r:reg_1_0A/\*dff.00.1\*', 'i:reg_1A');
set_user_match('r:reg_2_1A/\*dff.00.1\*', 'i:reg_1_0A/\*dff.00.0\*');


Note:
It is recommended to use SVF file, guide_multibit in SVF file has the same effect of this command

set_verbose

Run script in verbose mode

Usage:
set_verbose($num);
$num: Verbose level, higher to be more verbose

set_wireload

Command for Timing Report. Set wireload for one liberty library

Usage:
set_wireload($library, $wireload);
$library: Library name
$wireload: Wireload name


Examples:
#1. Set wireload for one library
set_wireload("TMC18VGB15ELV16S_1P8V_25C", "zero-wire-load-model");

set_write_verilog_remove_backslash

Enable write out verilog with backslash removal

Usage:
set_write_verilog_remove_backslash($value);
$value: 0, Disable by default
        1, Enable backslash removal in write_verilog

set_write_verilog_uniquify

Enable write out verilog in uniquified mode

Usage:
set_write_verilog_uniquify($value);
$value: 0, Disable by default
        1, Enable uniquify mode

set_xm_flop_merge_enable

Cross module flop mapping and merging enable. 

Usage:
set_xm_flop_merge_enable($setting,@options);
$setting: 0, disable cross module flop merge (default)
          1, enable cross module flop merge
@options:
   -parallel: Run merge process in parallel 

Note:
Flop merge inside module command set_flop_merge_enable is enabled by default

setup_eco

ECO command. Setup ECO

Usage:
setup_eco($eco_name, @options);
$eco_name: ECO name, like eco01234
@options:
    -help: Print this information.
    -comments comments: Comments to appear at the beginning of ECO netlist.


Examples:
#1. Setup ECO name 
setup_eco('eco1234')

#2. Setup ECO name with comments
setup_eco('eco1234', '-comments', 'Fix abc_state state machine');

source

Run Netlist processing script. 

Usage:
source($script_name);


Examples:
source("eco2.pl");


Note:
It has the same behavior as 'run' command

start_gui

Start GUI windows

Usage:
start_gui(@options);
@options:
   -source: Read in Reference RTL file if it exists
   -noblock: The process is not blocked by start_gui, by default the process is blocked by the GUI window

stitch_scan_chain

ECO command. Stitch scan chain

Usage:
stitch_scan_chain(@options);
@options:
   -to $flop_inst: Stitch all new flops into the flop_inst or stitch each module's new flops into one flop in this module 

Note:
If -to option doesn't exist, the new flops in each module are connected up in one chain and stitched into one existing scan flop 
  

Examples:
stitch_scan_chain("-to", "abc_reg"); # Insert new flops' scan chain into the existing flop 'abc_reg'
stitch_scan_chain();                 # Stitch the new flops into local scan chains

suppress_errors

Suppress error messages

Usage:
suppress_errors(@messages)
@messages: Error messages. 'E-001', 'E-132'

suppress_warnings

Suppress warning messages

Usage:
suppress_warnings(@messages)
@messages: Warning messages. 'W-001', 'W-002'


Examples:
suppress_warnings("W-001", "W-002", "W-003"); # Suppress these three warnings

swap_inst

ECO command. Swap two instances with same input/output pins.

Usage:
swap_inst($inst1, $inst2);
$inst1,$inst2: Swap these two instances.

Note:
$inst1 and $inst2 should have the same input/output pins.


Examples:
swap_inst("spare1/spr_and0", "spare2/spr_and1");

undo_eco

ECO command. Undo eco operations, restore the database to the original state.

Usage:
undo_eco();

verify_faults

GOF Formal only. Verify fault in stuck-0 or stuck-1 mode

Usage:
my $status = verify_faults($one_fault, @options);
$one_fault: Optional, to test one fault only 
@options:
   -help: Print this info
   -rough: Calculate SPFM/LFM only by structural COI analysis
   -full: Run full formal process in calculating SPFM/LFM
   -vcd vcd_file_name: Dump the sequence to the VCD file when $one_fault is defined
$status: Return 1 if a sequence exists


Examples:
#1. Check all fault in the whole design
verify_faults("-full");

#2. Check one fault stuck-0 and dump the sequence to the VCD file
verify_faults("u_master/U12/Y:0", "-vcd", "seq_u12.vcd");

verify_state

GOF Formal only. Verify if a sequence exists to set the signal

Usage:
my $status = verify_state(@sig_seq, @options);
@sig_seq: Signals and its value 
@options:
   -help: Print this info
   -or:  The signals are 'or' relationship, default 'and' relationship
   -vcd vcd_file_name: Dump the sequence to the VCD file when $one_fault is defined
$status: Return 1 if a sequence exists


Examples:
#1. Check one instance input A can be set to 0, dump to VCD file dump_seq.vcd 
verify_state("u_spi/U10/A:0", "-vcd", "dump_seq.vcd");

write_compare_points

Write all compare points to a report file

Usage:
write_compare_points($file_name, @options);
$file_name: The report file name
@options:
    -all:  Include name matching instances


Examples:
write_Compare_points("compare_points.rep"); # Write compare points with different naming
write_Compare_points("-all", "all_compare_points.rep"); # Write all compare points

write_dcsh

ECO command. Write ECO result in Design Compiler dcsh script format

Usage:
write_dcsh($dc_script_name);
$dc_script_name: Synopsys Design Compiler dcsh script name.


Examples:
write_dcsh("eco12345.dcsh");

write_formality_help_files

Write formality help files including mapped instance list and modified netlist files if necessary

Usage:
write_formality_help_files($help_name);
$help_name: Help name which can have directory specified


Note:
Examples:
#1. Write out Formality help files into directory fm_help with the base name eco_1225
write_formality_help_files("fm_help/eco_1225");

write_perl

ECO command to write ECO result in Perl script 

Usage:
write_perl($eco_script_name);
$eco_script_name: ECO script name

Note:
The command can be used after 'fix_design' API. Detail ECO operations are written out.

write_soce

ECO command. Write ECO result in Cadence SOC Encounter script format

Usage:
write_soce($soc_encounter_script_name, @options);
$soc_encounter_script_name: Cadence SOC Encounter script name.
@options:
    -type1: Alternate SOC Encounter script type


Examples:
write_soce("eco12345.soce");

write_spare_file

ECO command. Write spare cells list to a file

Usage:
write_spare_file($filename);
$filename: Spare cells file name to be written out


Note:
Any used spare cell has '#' in the start of the line

write_tcl

ECO command to write ECO result in Design Compiler tcl script format 

Usage:
write_tcl($tcl_script_name);
$tcl_script_name: Synopsys Design Compiler tcl script name.


Examples:
write_tcl("eco12345.tcl");

write_verilog

ECO command to write ECO result in Verilog netlist 

Usage:
write_verilog($verilog_file, @options);
@options:
    -help: Print this information
    -all:  Keep the modules in the netlist file even they are not the sub-modules of the top module
$verilog_file: The Verilog netlist file name, should be different from the existing Implementation Netlist file name.


Note:
When the Implementation design is read in by multiple netlist files, set_top command should be used to 
      make the correct file saved
      

Examples:
#1. Write out ECOed netlist to imp_eco.v
read_design("-ref", "reference.v");
read_design("-imp", "implementation.v");
fix_design;
write_verilog("imp_eco.v");

#2. The design is read in by command line 'gof -lib tsmc.lib ethernet_top.v'
#   After ECO, to write ECO netlist use command 
write_verilog("ethernet_top_eco.v");

#3. The design is read in by multiple netlist files in command line, 
#   'gof -lib tsmc.lib mem_control.v dsp.v ethernet_top.v'
#   The ECO is done on 'mem_control' module, to save the netlist
set_top("mem_control");
write_verilog("mem_control_eco.v");

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